Design steps towards a 40-kVA SiC inverter with an efficiency exceeding 99.5%
2012 (English)In: Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC, IEEE , 2012, 1536-1543 p.Conference paper (Refereed)
This paper describes the concept, the design, the construction, and experimental investigation of a 40 kVA inverter with Silicon Carbide Junction Field Effect Transistors. The inverter was designed to have an efficiency exceeding 99.5%. Due to the low losses free convection cooling could be used. Since no fans are used the reliability can be increased compared to solutions with fans. A very low conduction loss has been achieved by parallel connecting ten 85 mΩ normally-on JFETs in each switch position. A special gate-drive solution was applied forcing the transistors to switch very fast (approx. 20 kV/μs) resulting in very low switching losses. As the output power is almost equal to the input power a special effort was done to precisely determine the amount of semiconductor power losses via comparative thermal measurements. A detailed analysis of the measurements shows that the efficiency of the inverter is approximately 99.7% at 40 kVA.
Place, publisher, year, edition, pages
IEEE , 2012. 1536-1543 p.
, Annual IEEE Applied Power Electronics Conference and Exposition (APEC), ISSN 1048-2334
Exhibitions, Power electronics, Silicon carbide
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject SRA - Energy
IdentifiersURN: urn:nbn:se:kth:diva-92267DOI: 10.1109/APEC.2012.6166024ISI: 000309117700231ScopusID: 2-s2.0-84860184738ISBN: 978-145771215-9OAI: oai:DiVA.org:kth-92267DiVA: diva2:513061
27th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2012; Orlando, FL; 5 February 2012 through 9 February 2012
QC 201206272012-03-302012-03-302013-04-19Bibliographically approved