A GALS Network-on-Chip based on Rationally-Related Frequencies
2011 (English)In: 2011 IEEE 29TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), LOS ALAMITOS: IEEE COMPUTER SOC , 2011, 12-18 p.Conference paper (Refereed)
GALS Networks-on-Chip (NoCs) in which the frequency of every switch can be set independently would enable per-node DVFS without requiring asynchronous switch design. However, traditional GALS interfaces introduce high latency penalties and are therefore ill-suited for inter-switch links in a NoC. In this paper we introduce and study a GALS Network-on-Chip based on the Globally-Ratiochronous, Locally-Synchronous (GRLS) paradigm. GRLS constrains all switch frequencies to be rationally-related but enables the use of efficient interfaces which reduce the latency of the network 60% compared to GALS solutions and obtains better throughput-per-power ratios compared to synchronous and mesochronous solutions.
Place, publisher, year, edition, pages
LOS ALAMITOS: IEEE COMPUTER SOC , 2011. 12-18 p.
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-92456DOI: 10.1109/ICCD.2011.6081369ISI: 000298257400003ScopusID: 2-s2.0-83455235039ISBN: 978-1-4577-1952-3OAI: oai:DiVA.org:kth-92456DiVA: diva2:513896
IEEE 29th International Conference on Computer Design (ICCD)
QC 201204042012-04-042012-04-022012-04-04Bibliographically approved