high aspect ratio tsvs fabricated by magnetic self-assembly of gold-coated nickel wires
2012 (English)In: Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd, IEEE conference proceedings, 2012, 541-547 p.Conference paper (Refereed)
Three-dimensional (3D) integration is an emerging technologythat vertically interconnects stacked dies of electronics and/orMEMS-based transducers using through silicon vias (TSVs).TSVs enable the realization of devices with shorter signal lengths,smaller packages and lower parasitic capacitances, which can resultin higher performance and lower costs of the system. Inthis paper we demonstrate a new manufacturing technology forhigh-aspect ratio (> 8) through silicon metal vias using magneticself-assembly of gold-coated nickel rods inside etched throughsilicon-via holes. The presented TSV fabrication technique enablesthrough-wafer vias with high aspect ratios and superior electricalcharacteristics. This technique eliminates common issues inTSV fabrication using conventional approaches, such as the metaldeposition and via insulation and hence it has the potential to reducesignificantly the production costs of high-aspect ratio stateof-the-art TSVs for e.g. interposer, MEMS and RF applications.
Place, publisher, year, edition, pages
IEEE conference proceedings, 2012. 541-547 p.
, Electronic Components & Technology Conference. Proceedings, ISSN 0569-5503
Through-Silicon, Wafer, 3d, Technology, Vias, Lsis
Engineering and Technology
IdentifiersURN: urn:nbn:se:kth:diva-93494DOI: 10.1109/ECTC.2012.6248882ISI: 000309162000086ScopusID: 2-s2.0-84866328428ISBN: 978-1-4673-1965-2OAI: oai:DiVA.org:kth-93494DiVA: diva2:516584
62nd Electronic Components and Technology Conference (ECTC), May 29 - June 1, 2012, San Diego, CA
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QC 201206182012-06-182012-04-182012-11-30Bibliographically approved