Kinetic Modeling of Low Temperature Epitaxy Growth of SiGe Using Disilane and Digermane
2012 (English)In: Journal of the Electrochemical Society, ISSN 0013-4651, Vol. 159, no 5, H478-H481 p.Article in journal (Refereed) Published
Low temperature epitaxy (LTE) in Chemical Vapor Deposition (CVD) refers to 350-650 degrees C interval. This temperature range is critical for this process since the thermal and lattice mismatch (or strain relaxation) issues diminish in advanced BiCMOS processing. The modeling of the epitaxy process is a vital task to increase the understanding the growth process and to design any desired device structure. In this study, an empirical model for Si2H6/Ge2H6-based LTE of SiGe is developed and compared with experimental work. The model can predict the number of free sites on Si surface, growth rate of Si and SiGe, and the Ge content at low temperatures. A good agreement between the model and the experimental data is obtained.
Place, publisher, year, edition, pages
2012. Vol. 159, no 5, H478-H481 p.
Bi-CMOS, Device structures, Disilanes, Empirical model, Experimental data, Ge content, Growth process, Kinetic modeling, Low temperature epitaxies, Low temperatures, Si surfaces, Temperature range
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-95132DOI: 10.1149/2.jes113689ISI: 000302211800059ScopusID: 2-s2.0-84859327130OAI: oai:DiVA.org:kth-95132DiVA: diva2:526746
QC 201205152012-05-152012-05-142015-02-11Bibliographically approved