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TCP/IP Packet Flow Analyser
KTH, Superseded Departments, Teleinformatics. (CCSlab)
1999 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

This is the final version of my thesis project: TCP/IP Packet Flow Analyser. TCP/IP and ATM has been developed separately throughout the years. Each of them having their specific uses and advantages. Because of the fact that TCP/IP traffic rapidly increases it would be desirable to be able to serve TCP/IP traffic over an ATM network. This is done by wrapping TCP/IP datagrams in AAL5 frames.(ATM Adaptation Layer 5 frames).

As the volume of network traffic increases it has been essential in today’s fast moving and ever changing network environment for Network Managers to keep track of what is happening on their enterprise network. The Network Managers need this kind of “control” over the network traffic to be able to deliver cost effective solutions for increasing network bandwidth and better allocation of bandwidth to users, proactively monitor critical network links i.e links that are in need of more bandwidth or that are “abnormally” faulty, computing resources used by a host or host pairs, etc.

To be able to address these requirements and the fact that TCP/IP traffic is increasing, Ericsson Telecom AB which were developing an ATM Switch, called AXD 301, were very anxious to see if and how one can add the traffic flow analysing functionality to the switch by using an already existing circuit board. The design had to be adapted to the constrains of the circuit board, and thereby limited to a principle functionality of a traffic analyser. The analyser should also have the ability to send the collected data about the TCP/IP traffic to a regular work station equipped with an ATM card using a protocol specified by me.The functionality of the analyser was programmed in C and executed an embedded PowerPC.

The main insufficiency of the current design was the packet analysing speed. It was able to run with a bandwidth of approximately 114 to 240 Mbps. To improve the performance in a packet analysing speed point of view, some alternative ways to implement the analyser with more help from the hardware was proposed.

Place, publisher, year, edition, pages
1999. , 40 p.
National Category
Communication Systems
URN: urn:nbn:se:kth:diva-95441OAI: diva2:528325
Educational program
Master of Science in Engineering - Electrical Engineering
1999-01-15, Seminar room "Telegrafen", Isafjordsgatan 22, Kista, 14:00 (Swedish)
Available from: 2012-06-20 Created: 2012-05-24 Last updated: 2013-09-09Bibliographically approved

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