Generating and Analysing test pattern for ATM applications
Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
The essence of this Master's Thesis is to describe the way I have generate realistic traffic cases for ATM applications.
The base is made up by a Verilog program which is intended to communicate with the Switch Port Verilog code by transmitting and receiving ATM cell packets. The generation of cells is made in C code by using a Programming Language Interface provided by Cadence.
Several kind of isochronic services are described by using parameters in a three state Markovian Modulated Bernoulli Process with binomial distributed burst arrivals (MMBP/D/1-K Model). The model generates bursts which are put in separate input buffers for each source and are later polled by a round robin fashion.
Some of the parameters given in a previous work have been proven not to be in the allowable area for the probability. This has been noticed but not been further examined in this thesis.
The performance of the generator is about 240.000 cells per hour on a SUN Sparc Station 5 with 400 video teleconference sources.
Place, publisher, year, edition, pages
1996. , 31 p.
IdentifiersURN: urn:nbn:se:kth:diva-98047OAI: oai:DiVA.org:kth-98047DiVA: diva2:534660
Subject / course
Master of Science in Engineering - Electrical Engineering
1996-05-23, Seminar room at floor 5, elevator B, Isafjordsgatan 22, Kista, 17:00 (English)
Maguire Jr., Gerald Q., ProfessorShosha, Yehoshua
Maguire Jr., Gerald Q., Professor