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Design and Implementation of an Extendable SoC Virtual Platform in SystemC-TLM 2.0
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
2012 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

With the increasing design complexity for SoC development, the workload for hardware designer and verification engineer is becoming larger and larger. On the other hand, software and hardware development is unable to be carried out in parallel. This creates a bottleneck in the current design flow. Also, it will be very difficult to deal with the hardware problems which are found during the software development process. To overcome these problems, design at higher level needs to be applied. SystemC is a language which enables the design at the system level and the TLM-2.0 contains different standardized SystemC interface classes, which ensures the portability and interoperability of different IPs.

In this thesis, an extendable SoC virtual platform is implemented in SystemC. It can give exactly the same functions as the design specification required. A standardized SystemC module template is designed which owns all different interfaces of the virtual platform. The template can provide lots of convenience for future module development. One method for wrapping a C/C++ into SystemC is given and a basic framework structure is implemented so that the existing C++/Simics modules can work in the designed SystemC virtual platform. Finally, the comparison on simulation time and workload between RTL modules and SystemC modules is made, which demonstrates that large development time can be saved by using this virtual platform for software development.

Place, publisher, year, edition, pages
2012. , 53 p.
Trita-ICT-EX, 2012:39
National Category
Engineering and Technology
URN: urn:nbn:se:kth:diva-98661OAI: diva2:538311
Available from: 2012-06-29 Created: 2012-06-29 Last updated: 2012-06-29Bibliographically approved

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