Low-latency no-handshake GALS interfaces for fast-receiver links
2012 (English)In: Proceedings of the IEEE International Conference on VLSI Design, IEEE , 2012, 191-196 p.Conference paper (Refereed)
In this paper we introduce a novel interface for Globally-Asynchronous, Locally-Synchronous systems which does not use any form of handshake to cross the gap between the clock domains. In particular, links in which the Receiver runs faster than the Transmitter are targeted. The interface works by finding an approximate ratio between the clock frequencies. Then, ratiochronous synchronizers that can tolerate clock drifts are employed to transmit data from the Transmitter to the Receiver clock domain. Thanks to the periodic properties of rationally-related systems, no handshake is employed and the average latency of the interface is decreased âˆŒ 75% compared to state-of-the-art GALS interfaces. Additionally, the interface uses only standard cells and, save for a delay line, can be designed at Register Transfer Level.
Place, publisher, year, edition, pages
IEEE , 2012. 191-196 p.
, International Conference on VLSI Design. Proceedings, ISSN 1063-9667
Approximate ratio, Clock domains, Clock drift, Clock frequency, Low-latency, Periodic properties, Register transfer level, Standard cell, Transmit data, Clocks, Electric batteries, Transmitters, Wireless sensor networks, Embedded systems
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-98578DOI: 10.1109/VLSID.2012.69ScopusID: 2-s2.0-84859909892ISBN: 978-076954638-4OAI: oai:DiVA.org:kth-98578DiVA: diva2:538377
25th International Conference on VLSI Design, VLSID 2012 and the 11th International Conference on Embedded Systems; Hyderabad;7 January 2012 through 11 January 2012
QC 201206292012-06-292012-06-282012-06-29Bibliographically approved