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Fast Viterbi Decoder Algorithms for Multi-Core System
KTH, School of Electrical Engineering (EES), Signal Processing.
2012 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

In this thesis, fast Viterbi Decoder algorithms for a multi-core system are studied. New parallel Viterbi algorithms for decoding convolutional codes are proposed based on tail biting trellises. The performances of the new algorithms are first evaluated by MATLAB and then Eagle (E-UTRA algorithms for LTE) link level simulations where the optimal parameter settings are obtained based on various simulations. One of the algorithms is proposed for implementation in the product due to its good BLER performance and low implementation complexity.

The new parallel algorithm is then implemented on target DSPs for Ericsson internal multi-core system to decode the PUSCH (Physical Uplink Shared Channel) CQI (Channel Quality Indicator) in LTE (Long Term Evolution). And the performance of the new algorithm in the real multi-core system is compared against the current implementation regarding both cycle and memory consumption. As a fast decoder, the proposed parallel Viterbi decoder is computationally efficient which reduces significantly the decoding latency and solves memory limitation problems on DSP.

Place, publisher, year, edition, pages
2012. , 47 p.
EES Examensarbete / Master Thesis, XR-EE-SB 2012:014
Keyword [en]
Parallel algorithm, Viterbi algorithm, Tail biting convolutional code, Multi-core
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
URN: urn:nbn:se:kth:diva-98779OAI: diva2:538966
Educational program
Master of Science - Wireless Systems
Available from: 2012-07-02 Created: 2012-07-02 Last updated: 2012-07-02Bibliographically approved

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