A highly linear 1.2 V 12bit 5-45 MS/s CMOS pipelined ADC with CM-sensing-and-input-interchanged OTA sharing
2012 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 72, no 1, 237-241 p.Article in journal (Refereed) Published
A 1.2 V 12bit programmable pipelined ADC is presented and implemented in 0.13 mu m CMOS technology. A common-mode-sensing-and-input-interchanged OTA-sharing technique is proposed to address the non-resetting and successive-stage crosstalk issues in conventional OTA-sharing technique. Speed options of 5-45 MS/s are available with scalable power obtained by adjusting the bias currents for OTAs, comparators, and reference buffers, etc., or the global bias current. The measured signal-to-distortion-and-noise ratio is in range of 62.5-69.2 dB, and the peak spurious free dynamic range is 80.7 dB for all speed options, while the figure-of-merit is in the range of 0.26-0.49 pJ/conversion. The core area is 1.5 mm(2).
Place, publisher, year, edition, pages
2012. Vol. 72, no 1, 237-241 p.
Pipelined ADC, OTA sharing, CM-sensing-and-input-interchanged, Programmable
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-98709DOI: 10.1007/s10470-012-9829-4ISI: 000304874300025ScopusID: 2-s2.0-84861891357OAI: oai:DiVA.org:kth-98709DiVA: diva2:539522
QC 201207032012-07-042012-07-022016-01-27Bibliographically approved