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Drift-free micromirror arrays made of monocrystalline silicon for adaptive optics applications
KTH, School of Electrical Engineering (EES), Microsystem Technology.
Fraunhofer IPMS.
KTH, School of Electrical Engineering (EES), Microsystem Technology.ORCID iD: 0000-0001-9552-4234
Fraunhofer IPMS.
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2012 (English)In: Journal of microelectromechanical systems, ISSN 1057-7157, E-ISSN 1941-0158, Vol. 21, no 4, 959-970 p.Article in journal (Refereed) Published
Abstract [en]

In this paper, we report on the heterogeneous integration of monocrystalline silicon membranes for the fabrication of large segmented micromirror arrays for adaptive optics applications. The design relies on a one-level architecture with mirrors and suspension formed within the same material, employing a large actuator gap height of up to 5.1 μ m to allow for a piston-type mirror deflection of up to 1600 nm. Choosing monocrystalline silicon as actuator and mirror material, we demonstrate a completely drift-free operation capability. Furthermore, we investigate stress effects that degrade the mirror topography, and we show that the stress originates from the donor silicon-on-insulator wafer. The novel heterogeneous integration strategy used in this work is capable of reducing this stress to a large extent.

Place, publisher, year, edition, pages
2012. Vol. 21, no 4, 959-970 p.
Keyword [en]
Heterogeneous integration, mirrors, silicon, spatial light modulators (SLMs), very large scale integration, wafer bonding, wafer-scale integration
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:kth:diva-99161DOI: 10.1109/JMEMS.2012.2190713ISI: 000307124200026Scopus ID: 2-s2.0-84864579675OAI: oai:DiVA.org:kth-99161DiVA: diva2:541186
Funder
EU, European Research Council
Note

QC 20120830

Available from: 2012-07-15 Created: 2012-07-15 Last updated: 2017-12-07Bibliographically approved
In thesis
1. Wafer-level 3-D CMOS Integration of Very-large-scale Silicon Micromirror Arrays and Room-temperature Wafer-level Packaging
Open this publication in new window or tab >>Wafer-level 3-D CMOS Integration of Very-large-scale Silicon Micromirror Arrays and Room-temperature Wafer-level Packaging
2013 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

This thesis describes the development of wafer-level fabrication and packaging methods for micro-electromechanical (MEMS) devices, based on wafer-bonding.

The first part of the thesis is addressing the development of a wafer-level technology that allows the use of high performance materials, such as monocrystalline silicon, for MEMS devices that are closely integrated on top of sensitive integrated circuits substrates. Monocrystalline silicon has excellent mechanical properties that are hard to achieve otherwise, and therefore it fits well in devices for adaptive optics and maskwriting applications where nanometer precision deflection requirements call for mechanically stable materials. However, the temperature sensitivity of the integrated circuits prohibits the use of monocrystalline silicon with conventional deposition and surface micromachining techniques. Here, heterogeneous 3-D integration by adhesive wafer-bonding is used to fabricate three different types of spatial light modulators, based on micromirror arrays made of monocrystalline silicon; micromirror arrays with vertically moving “piston-type” mirrors and with tilting mirrors made of one functional monocrystalline silicon layer, and vertically moving hidden-hinge micromirror arrays made of two functional monocrystalline silicon layers.

The second part of the thesis addresses the need for room-temperature packaging methods that allow the packaging of liquids or in general heat sensitive devices on wafer-level. A packaging method was developed that is based on a hybrid wafer-bonding approach, combining the compression bonding of gold gaskets with adhesive bonding. The packaging method is first demonstrated for the wafer-level encapsulation of liquids in reservoirs and then applied to packaging a dye-based photonic gas sensor.

 

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2013. xi, 126 p.
Series
Trita-EES, 2013:031
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-125913 (URN)978-91-7501-843-0 (ISBN)
Public defence
2013-09-06, F3, Lindstedtsvägen 26, KTH, Stockholm, 14:14 (English)
Opponent
Supervisors
Note

QC 20130816

Available from: 2013-08-16 Created: 2013-08-16 Last updated: 2013-08-19Bibliographically approved

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Stemme, GöranNiklaus, Frank

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