Impact of oxidation and reduction annealing on the electrical properties of Ge/La2O3/ZrO2 gate stacks
2012 (English)In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 74, 7-12 p.Article in journal (Refereed) Published
The paper addresses the passivation of Germanium surfaces by using layered La2O3/ZrO2 high-k dielectrics deposited by Atomic Layer Deposition to be applied in Ge-based MOSFET devices. Improved electrical properties of these multilayered gate stacks exposed to oxidizing and reducing ambient during thermal post treatment in presence of thin Pt cap layers are demonstrated. The results suggest the formation of thin intermixed LaxGeyOz interfacial layers with thicknesses controllable by oxidation time. This formation is further investigated by XPS, EDX/EELS and TEM analysis. An additional reduction annealing treatment further improves the electrical properties of the gate dielectrics in contact with the Ge substrate. As a result low interface trap densities on (100) Ge down to 3 x 10(11) eV(-1) cm(-2) are demonstrated. The formation of the high-k LaxGeyOz, layer is in agreement with the oxide densification theory and may explain the improved interface trap densities. The scaling potential of the respective layered gate dielectrics used in Ge-based MOS-based device structures to EOT of 1.2 nm or below is discussed. A trade-off between improved interface trap density and a lowered equivalent oxide thickness is found.
Place, publisher, year, edition, pages
2012. Vol. 74, 7-12 p.
High-k, La2O3, ZrO2, Annealing, Oxidation, Germanate, Germanium
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-99215DOI: 10.1016/j.sse.2012.04.004ISI: 000305728600003ScopusID: 2-s2.0-84861878551OAI: oai:DiVA.org:kth-99215DiVA: diva2:542003
QC 201207272012-07-272012-07-232013-10-01Bibliographically approved