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Modeling and power evaluation of on-chip router components in spintronics
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0061-3475
2012 (English)In: Proceedings of the 2012 6th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2012, IEEE , 2012, 51-58 p.Conference paper, Published paper (Refereed)
Abstract [en]

On-chip routers are power hungry components. Besides exploiting current CMOS-based power-saving techniques, it is also desirable to investigate the power saving potential enabled by new technologies and devices. This paper investigates the potential of exploiting the emerging spin-electronics based MTJ (Magnetic Tunnel Junction) devices with application to on-chip router modules, in particular, buffers and crossbars. To this end, we build MTJ models, design circuits based on mixed MTJ-CMOS devices, and evaluate their switching power consumption, using their pure CMOS counterparts as the baseline. Our study shows that the new technology can significantly improve power efficiency for buffers but the gain for crossbars is less clear.

Place, publisher, year, edition, pages
IEEE , 2012. 51-58 p.
Keyword [en]
MTJ, Network-on-Chip (NoC), Router, Spintronics
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-100508DOI: 10.1109/NOCS.2012.13Scopus ID: 2-s2.0-84862731015ISBN: 978-076954677-3 (print)OAI: oai:DiVA.org:kth-100508DiVA: diva2:543812
Conference
2012 6th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2012; Copenhagen; 9 May 2012 through 11 May 2012
Note

QC 20120810

Available from: 2012-08-10 Created: 2012-08-09 Last updated: 2013-09-16Bibliographically approved

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Lu, Zhonghai

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  • apa
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