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A single-cycle output buffered router with layered switching for Networks-on-Chips
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0061-3475
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2012 (English)In: Computers & electrical engineering, ISSN 0045-7906, E-ISSN 1879-0755, Vol. 38, no 4, 906-916 p.Article in journal (Refereed) Published
Abstract [en]

We present a single-cycle output buffered router based on layered switching for networks on chips (NoCs). Different from state-of-the-art NoC routers, the router has three important characteristics: (1) It employs layered switching, which implements wormhole on top of virtual cut-through (VCT) switching; (2) In contrast to input buffered architectures, it adopts an output buffered architecture; (3) It is single cycle, meaning that the router pipeline takes only one cycle for all flits. Experimental results show that the router achieves up to 80% of ideal network throughput under uniform random traffic pattern. Compared with wormhole switching, layered switching achieves up to 36.9% latency reduction for 12-flit packets under uniform random traffic with an injection rate of 0.5 flit/cycle/node. Under 65 nm technology synthesized results show that its critical path has only 20 logic gates, and it reduces 11% area compared to the input virtual-channel router with the same buffer capacity.

Place, publisher, year, edition, pages
2012. Vol. 38, no 4, 906-916 p.
Keyword [en]
Microprocessor chips, Network architecture, Routers, Switching
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
URN: urn:nbn:se:kth:diva-100612DOI: 10.1016/j.compeleceng.2012.02.018ISI: 000306391600009ScopusID: 2-s2.0-84862222382OAI: diva2:543986
QC 20120813Available from: 2012-08-13 Created: 2012-08-13 Last updated: 2012-08-13Bibliographically approved

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Lu, Zhonghai
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