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Very high aspect ratio through-silicon vias (TSVs) fabricated using automated magnetic assembly of nickel wires
KTH, School of Electrical Engineering (EES), Microsystem Technology.ORCID iD: 0000-0003-3452-6361
KTH, School of Electrical Engineering (EES), Microsystem Technology.ORCID iD: 0000-0002-4867-0391
KTH, School of Electrical Engineering (EES), Microsystem Technology.ORCID iD: 0000-0002-0441-6893
KTH, School of Electrical Engineering (EES), Microsystem Technology.
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2012 (English)In: Journal of Micromechanics and Microengineering, ISSN 0960-1317, E-ISSN 1361-6439, Vol. 22, no 10, 105001- p.Article in journal (Refereed) Published
Abstract [en]

Through-silicon via (TSV) technology enables 3D-integrated devices with higher performance and lower cost as compared to 2D-integrated systems. This is mainly due to smaller dimensions of the package and shorter internal signal lengths with lower capacitive, resistive and inductive parasitics. This paper presents a novel low-cost fabrication technique for metal-filled TSVs with very high aspect ratios (>20). Nickel wires are placed in via holes of a silicon wafer by an automated magnetic assembly process and are used as a conductive path of the TSV. This metal filling technique enables the reliable fabrication of through-wafer vias with very high aspect ratios and potentially eliminates characteristic cost drivers in the TSV production such as advanced metallization processes, wafer thinning and general issues associated with thin-wafer handling.

Place, publisher, year, edition, pages
Institute of Physics (IOP), 2012. Vol. 22, no 10, 105001- p.
Keyword [en]
Electronics packaging, Silicon wafers, Wire
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:kth:diva-101062DOI: 10.1088/0960-1317/22/10/105001ISI: 000309219500001Scopus ID: 2-s2.0-84866321637OAI: oai:DiVA.org:kth-101062DiVA: diva2:546126
Funder
EU, European Research Council, 277879
Note

QC 20120827

Available from: 2012-08-27 Created: 2012-08-22 Last updated: 2017-12-07Bibliographically approved
In thesis
1. Integration and Fabrication Techniques for 3D Micro- and Nanodevices
Open this publication in new window or tab >>Integration and Fabrication Techniques for 3D Micro- and Nanodevices
2012 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The development of micro and nano-electromechanical systems (MEMS and NEMS) with entirely new or improved functionalities is typically based on novel or improved designs, materials and fabrication methods. However, today’s micro- and nano-fabrication is restrained by manufacturing paradigms that have been established by the integrated circuit (IC) industry over the past few decades. The exclusive use of IC manufacturing technologies leads to limited material choices, limited design flexibility and consequently to sub-optimal MEMS and NEMS devices. The work presented in this thesis breaks new ground with a multitude of novel approaches for the integration of non-standard materials that enable the fabrication of 3D micro and nanoelectromechanical systems. The objective of this thesis is to highlight methods that make use of non-standard materials with superior characteristics or methods that use standard materials and fabrication techniques in a novel context. The overall goal is to propose suitable and cost-efficient fabrication and integration methods, which can easily be made available to the industry.

The first part of the thesis deals with the integration of bulk wire materials. A novel approach for the integration of at least partly ferromagnetic bulk wire materials has been implemented for the fabrication of high aspect ratio through silicon vias. Standard wire bonding technology, a very mature back-end technology, has been adapted for yet another through silicon via fabrication method and applications including liquid and vacuum packaging as well as microactuators based on shape memory alloy wires. As this thesis reveals, wire bonding, as a versatile and highly efficient technology, can be utilized for applications far beyond traditional interconnections in electronics packaging.

The second part presents two approaches for the 3D heterogeneous integration based on layer transfer. Highly efficient monocrystalline silicon/ germanium is integrated on wafer-level for the fabrication of uncooled thermal image sensors and monolayer-graphene is integrated on chip-level for the use in diaphragm-based pressure sensors.

The last part introduces a novel additive fabrication method for layer-bylayer printing of 3D silicon micro- and nano-structures. This method combines existing technologies, including focused ion beam implantation and chemical vapor deposition of silicon, in order to establish a high-resolution fabrication process that is related to popular 3D printing techniques.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2012. xv, 91 p.
Series
TRITA-EE, ISSN 1653-5146 ; 2013:001
Keyword
Microelectromechanical systems, MEMS, Nanoelectromechanical systems, NEMS, silicon, wafer-level, chip-level, through silicon via, TSV, packaging, 3D packaging, vacuum packaging, liquid encapsulation, integration, heterogeneous integration, wafer bonding, microactuators, shape memory alloy, SMA, wire bonding, magnetic assembly, self-assembly, 3D, 3D printing, focused ion beam, FIB
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-107125 (URN)978-91-7501-583-5 (ISBN)
Public defence
2013-01-18, F3, Lindstedtsvägen 26, KTH, Stockholm, 10:00 (English)
Opponent
Supervisors
Note

QC 20121207

Available from: 2012-12-07 Created: 2012-12-06 Last updated: 2016-08-11Bibliographically approved
2. Heterogeneous 3D Integration and Packaging Technologies for Nano-Electromechanical Systems
Open this publication in new window or tab >>Heterogeneous 3D Integration and Packaging Technologies for Nano-Electromechanical Systems
2017 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Three-dimensional (3D) integration of micro- and nano-electromechanical systems (MEMS/NEMS) with integrated circuits (ICs) is an emerging technology that offers great advantages over conventional state-of-the-art microelectronics. MEMS and NEMS are most commonly employed as sensor and actuator components that enable a vast array of functionalities typically not attainable by conventional ICs. 3D integration of NEMS and ICs also contributes to more compact device footprints, improves device performance, and lowers the power consumption. Therefore, 3D integration of NEMS and ICs has been proposed as a promising solution to the end of Moore’s law, i.e. the slowing advancement of complementary metal-oxide-semiconductor (CMOS) technology.In this Ph.D. thesis, I propose a comprehensive fabrication methodology for heterogeneous 3D integration of NEM devices directly on top of CMOS circuits. In heterogeneous integration, the NEMS and CMOS components are fully or partially fabricated on separate substrates and subsequently merged into one. This enables process flexibility for the NEMS components while maintaining full compatibility with standard CMOS fabrication. The first part of this thesis presents an adhesive wafer bonding method using ultra-thin intermediate bonding layers which is utilized for merging the NEMS components with the CMOS substrate. In the second part, a novel NEM switch concept is introduced and the performance of CMOS-integrated NEM switch circuits for logic and computation applications is discussed. The third part examines two different packaging approaches for integrated MEMS and NEMS devices with either hermetic vacuum cavities or low-cost glass lids for optical applications. Finally, a novel fabrication approach for through silicon vias (TSVs) by magnetic assembly is presented, which is used to establish an electrical connection from the packaged devices to the outside world.

Abstract [sv]

Tredimensionell (3D) integration av mikro- och nano-elektromekaniska system (MEMS/NEMS) med integrerade kretsar (ICs) är en ny teknik som erbjuder stora fördelar jämfört med konventionell mikroelektronik. MEMS och NEMS används oftast som sensorer och aktuatorer då de möjliggör många funktioner som inte kan uppnås med vanliga ICs.3D-integration av NEMS och ICs bidrar även till mindre dimensioner, ökade prestanda och mindre energiförbrukning av elektriska komponenter. Den nuvarande tekniken för complementary metal-oxide-semicondictor (CMOS) närmar sig de fundamentala gränserna vilket drastiskt begränsar utvecklingsmöjligheten för mikroelektronik och medför slutet på Moores lag. Därför har 3D-integration identifierats som en lovande teknik för att kunna driva vidare utvecklingen för framtidens elektriska komponenter.I denna avhandling framläggs en omfattande fabrikationsmetodik för heterogen 3D-integration av NEMS ovanpå CMOS-kretsar. Heterogen integration betyder att både NEMS- och CMOS-komponenter byggs på separata substrat för att sedan förenas på ett enda substrat. Denna teknik tillåter full processfrihet för tillverkning av NEMS-komponenter och garanterar kompatibilitet med standardiserade CMOS-fabrikationsprocesser.I den första delen av avhandlingen beskrivs en metod för att sammanfoga två halvledarskivor med en extremt tunn adhesiv polymer. Denna metod demonstreras för 3D-integration av NEMS- och CMOS-komponenter. Den andra delen introducerar ett nytt koncept för NEM-switchar och dess användning i NEM-switch-baserade mikrodatorchip. Den tredje delen presenterar två olika inkapslingsmetoder för MEMS och NEMS. Den ena metoden fokuserar på hermetisk vakuuminkapsling medan den andra metoden beskriver en lågkostnadsstrategi för inkapsling av optiska komponenter. Slutligen i den fjärde delen presenteras en ny fabrikationsteknik för så kallade ”through silicon vias” (TSVs) baserad på magnetisk självmontering av nickeltråd på mikrometerskala.

Place, publisher, year, edition, pages
KTH Royal Institute of Technology, 2017. 55 p.
Series
TRITA-EE, ISSN 1653-5146 ; 2017:048
Keyword
Nano-electromechanical systems (NEMS), Micro-electromechanical systems (MEMS), heterogeneous 3D integration, CMOS integration, Morethan- Moore (MtM), adhesive wafer bonding, NEM switch, FPGA, contact reliability, hermetic vacuum packaging, Cu low-temperature welding, through silicon vias (TSVs), magnetic self-assembly
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-207185 (URN)978-91-7729-431-3 (ISBN)
Public defence
2017-06-15, Q2, Osquldas väg 10, Stockholm, 10:00 (English)
Opponent
Supervisors
Note

20170519

Available from: 2017-05-19 Created: 2017-05-18 Last updated: 2017-05-19Bibliographically approved

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Fischer, Andreas C.Bleiker, Simon J.Haraldsson, TommyStemme, GöranNiklaus, Frank

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