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Distributed Memory Architecture with Hardware Graph Array for Configuring the Network Interconnections.
KTH, School of Information and Communication Technology (ICT).
2012 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

The Network-on-chip is considered to be a promising architecture with the advent of increase in the integration of the distributed processing elements. The conflict of data transfer through the network became an urgent issue that need to be solved. DiMArch is an existing distributed memory architecture that can solve the data transfer conflict at compile time. This thesis extends DiMArch with a centralized Network-on-Chip manager called HDiMArch, this architecture monitor the memory accessibility and create data interconnection path with hardware. The conflict which occurred at runtime is resolved by establish the Hardware graph array.

The HDiMArch is synthesized using TSMC 90nm with different parameters. Area, power and maximum power results are analyzed.

Place, publisher, year, edition, pages
2012. , 51 p.
Series
Trita-ICT-EX, 2012:208
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:kth:diva-102812OAI: oai:DiVA.org:kth-102812DiVA: diva2:556742
Educational program
Master of Science - System-on-Chip Design
Uppsok
Technology
Supervisors
Examiners
Available from: 2012-09-26 Created: 2012-09-26 Last updated: 2012-09-26Bibliographically approved

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CiteExportLink to record
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Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf