The Role of the Parasitic Capacitance of the Inductorin Boost Converters with Normally-On SiC JFETs
2012 (English)In: 2012 7th International Power Electronics and Motion Control Conference (IPEMC), IEEE conference proceedings, 2012, 1842-1847 p.Conference paper, Poster (Refereed)
In this paper the impact of the parasitic capacitance ofthe inductor on the performance of a fast-switching boostconverters with SiC JFETs is discussed. Two inductor designs,one conventional and another with a space between the windinglayers, are investigated and their parasitic capacitances aremeasured by different methods. The air-gap between the windinglayers reduced the inductor self-capacitance more than 8 times.The two inductors were used in a 2 kW, 100 kHz boost converterwith a normally-on SiC JFET and their performance wascompared. When the inductor with a low self-capacitance wasused, there were fewer oscillations during the switchingtransients and the losses were reduced about 16 %.
Place, publisher, year, edition, pages
IEEE conference proceedings, 2012. 1842-1847 p.
Silicon carbide, parasictic capacitanse, inductor design, DC-DC converter, Silicon Carbide, JFET
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-103053DOI: 10.1109/IPEMC.2012.6259118ScopusID: 2-s2.0-84866778214ISBN: 978-1-4577-2085-7OAI: oai:DiVA.org:kth-103053DiVA: diva2:558144
2012 IEEE 7th International Power Electronics and Motion Control Conference - ECCE Asia June 2-5, 2012, Harbin, China
QC 201210052012-10-052012-10-022012-10-05Bibliographically approved