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Design and Evaluation of Reduced Self-Capacitance Inductor for Fast-Switching SiC BJTdc/dc Converters
Warsaw University of Technlogy.
KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
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2012 (English)In: Power Electronics and Motion Control Conference (EPE/PEMC), 2012 15th International, IEEE , 2012, DS1a.41-DS1a.47 p.Conference paper, Published paper (Refereed)
Abstract [en]

The paper presents design, measurements and evaluation of the inductor with reduced self-capacitance. As an reference inductor with the same parameters but non-optimized self-capacitance is chosen. Differences in the parasitic capacitance of the inductor are validated by four measurement methods and experimentally confirmed on a 2 kW, 100 kHz dc/dc converter with silicon carbide BJTs. When the low-capacitance inductor is applied the switching performance is better, especially high-frequency resonances are limited. Additionally, it was found that the power losses were reduced by approximately 20%.

Place, publisher, year, edition, pages
IEEE , 2012. DS1a.41-DS1a.47 p.
Keyword [en]
Silicon carbide, parasitic capacitance, dc/dc converters
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-103054DOI: 10.1109/EPEPEMC.2012.6397194Scopus ID: 2-s2.0-84874273048ISBN: 978-146731971-3 (print)OAI: oai:DiVA.org:kth-103054DiVA: diva2:558152
Conference
15th International Power Electronics and Motion Control Conference and Exposition, EPE-PEMC 2012 ECCE Europe;Novi Sad;4 September 2012 through 6 September 2012
Note

QC 20121005

Available from: 2012-10-05 Created: 2012-10-02 Last updated: 2013-03-04Bibliographically approved

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Nee, Hans-Peter

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CiteExportLink to record
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Citation style
  • apa
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Language
  • de-DE
  • en-GB
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  • nn-NB
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  • Other locale
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Output format
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