Power distribution TSVs induced core switching noise
2011 (English)In: Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), 2010 IEEE, IEEE conference proceedings, 2011Conference paper (Refereed)
Size of on-chip interconnects as well as the supply voltage is reducing with each technology node whereas the operating speed is increasing in modern VLSI design. Today, the package inductance and resistance has been reduced to such an extent that core switching noise caused by on-chip inductance and on-chip resistance is gaining importance as compared to I/O drivers switching noise. Both on-chip inductance and skin effect are prime players at frequencies of the order of GHz. The problem is further aggravated when chips are interconnected through TSVs to form a 3D integrated stack in order to achieve low form factor and high integration density. In this paper we analysed peak core switching noise in a 3D stack of integrated chips interconnected through power distribution TSV pairs, through our comprehensive mathematical model which has been proved to be quite accurate as compared to SPICE. We analysed the effect of number of chips in a 3D stack, rise time, decoupling capacitance, and skin effect on power distribution TSVs induced core switching noise in this paper.
Place, publisher, year, edition, pages
IEEE conference proceedings, 2011.
3D stack, Core switching noise, Rise time, Skin effect
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-103557DOI: 10.1109/EDAPS.2010.5683008ScopusID: 2-s2.0-79851475832ISBN: 978-1-4244-9069-1OAI: oai:DiVA.org:kth-103557DiVA: diva2:560463
Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), 2010 IEEE, Singapore
QC 201210152012-10-152012-10-152013-04-23Bibliographically approved