Decoupling capacitance for the power integrity of 3D-DRAM-over-logic system
2012 (English)In: IEEE 13th Electronics Packaging Technology Conference (EPTC), 2011, IEEE conference proceedings, 2012, 590-594 p.Conference paper (Refereed)
The 3D-DRAM stacked over the processor is a vibrant technique in order to overcome the memory wall as well as the bandwidth wall problems. We considered a system with two DRAM dies over a single processor die. We assumed the decoupling capacitors to be placed on each DRAM die and connected to the power distribution TSV pairs, where the TSVs pass through the DRAM stack. In this paper we proposed a mathematical model for the optimum value of the decoupling capacitance on each DRAM die along with the optimum values of the effective resistance of the interconnecting power distribution TSV pairs in order to ensure the power integrity of the logic load during switching. The proposed model has a maximum of 1.1% error as compared to the Ansoft Nexxim4.1.
Place, publisher, year, edition, pages
IEEE conference proceedings, 2012. 590-594 p.
3D-DRAM, Decoupling capacitance, Power integrity
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-103560DOI: 10.1109/EPTC.2011.6184489ScopusID: 2-s2.0-84860909009ISBN: 978-1-4577-1981-3OAI: oai:DiVA.org:kth-103560DiVA: diva2:560475
IEEE 13th Electronics Packaging Technology Conference (EPTC), 2011, Singapore
QC 201210152012-10-152012-10-152013-04-23Bibliographically approved