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Decoupling capacitance for the power integrity of 3D-DRAM-over-logic system
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
2012 (English)In: IEEE 13th Electronics Packaging Technology Conference (EPTC), 2011, IEEE conference proceedings, 2012, 590-594 p.Conference paper, Published paper (Refereed)
Abstract [en]

The 3D-DRAM stacked over the processor is a vibrant technique in order to overcome the memory wall as well as the bandwidth wall problems. We considered a system with two DRAM dies over a single processor die. We assumed the decoupling capacitors to be placed on each DRAM die and connected to the power distribution TSV pairs, where the TSVs pass through the DRAM stack. In this paper we proposed a mathematical model for the optimum value of the decoupling capacitance on each DRAM die along with the optimum values of the effective resistance of the interconnecting power distribution TSV pairs in order to ensure the power integrity of the logic load during switching. The proposed model has a maximum of 1.1% error as compared to the Ansoft Nexxim4.1.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2012. 590-594 p.
Keyword [en]
3D-DRAM, Decoupling capacitance, Power integrity
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-103560DOI: 10.1109/EPTC.2011.6184489Scopus ID: 2-s2.0-84860909009ISBN: 978-1-4577-1981-3 (print)OAI: oai:DiVA.org:kth-103560DiVA: diva2:560475
Conference
IEEE 13th Electronics Packaging Technology Conference (EPTC), 2011, Singapore
Note

QC 20121015

Available from: 2012-10-15 Created: 2012-10-15 Last updated: 2013-04-23Bibliographically approved
In thesis
1. Core Switching Noise for On-Chip 3D Power Distribution Networks
Open this publication in new window or tab >>Core Switching Noise for On-Chip 3D Power Distribution Networks
2012 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Reducing the interconnect size with each technology node and increasing speed with each generation increases IR-drop and Ldi/dt noise. In addition to this, the drive for more integration increases the average current requirement for modern ULSI design. Simultaneous switching of core logic blocks and I/O drivers produces large current transients due to power distribution network parasitics at high clock frequency. The current transients are injected into the power distribution planes thereby inducing noise in the supply voltage. The part of the noise that is caused by switching of the internal logic load is core switching noise. The core logic switches at much higher speed than driver speed whereas the package inductance is less than the on-chip inductance in modern BGA packages. The core switching noise is currently gaining more attention for three-dimensional integrated circuits where on-chip inductance is much higher than the board and package inductance due to smaller board, and package. The switching noise of the driver is smaller than the core switching noise due to small driver size and reduced capacitance associated with short on-board wires for three-dimensional integrated circuits. The load increases with the addition of each die. The power distribution TSV pairs to supply each extra die also introduce additional parasitic. The core switching noise may propagate through substrate and consequently through interconnecting TSVs to different dies in heterogeneous integrated system. Core switching noise may lead to decreased device drive capability, increased gate delays, logic errors, and reduced noise margins. The actual behavior of the on-chip load is not well known in the beginning of the design cycle whereas altering the design during later stages is not cost effective. The size of a three-dimensional power distribution network may reach billions of nodes with the addition of dies in a vertical stack. The traditional tools may run out of time and memory during simulation of a three-dimensional power distribution network whereas, the CAD tools for the analysis of 3D power distribution network are in the process of evolution. Compact mathematical models for the estimation of core switching noise are necessary in order to overcome the power integrity challenges associated with the 3D power distribution network design. This thesis presents three different mathematical models to estimate core switching noise for 3D stacked power distribution networks. A time-domain-based mathematical model for the estimation of design parameters of a power distribution TSV pair is also proposed. Design guidelines for the estimation of optimum decoupling capacitance based on flat output impedance are also proposed for each stage of the vertical chain of power distribution TSV pairs. A mathematical model for tradeoff between TSV resistance and amount of decoupling capacitance on each DRAM die is proposed for a 3D-DRAM-Over-Logic system. The models are developed by following a three step approach: 1) design physical model, 2) convert it to equivalent electrical model, and 3) formulate the mathematical model based on the electrical model. The accuracy, speed and memory requirement of the proposed mathematical model is compared with equivalent Ansoft Nexxim models.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2012. xxviii, 108 p.
Series
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 12:06
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-103566 (URN)978-91-7501-519-4 (ISBN)
Public defence
2012-11-07, Sal/Hal Sal E, Forum, KTH-ICT, Isafjordsgatan 39, Kista, 09:00 (English)
Opponent
Supervisors
Note

QC 20121015

Available from: 2012-10-15 Created: 2012-10-15 Last updated: 2012-10-15Bibliographically approved

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