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Core Switching Noise for On-Chip 3D Power Distribution Networks
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
2012 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Reducing the interconnect size with each technology node and increasing speed with each generation increases IR-drop and Ldi/dt noise. In addition to this, the drive for more integration increases the average current requirement for modern ULSI design. Simultaneous switching of core logic blocks and I/O drivers produces large current transients due to power distribution network parasitics at high clock frequency. The current transients are injected into the power distribution planes thereby inducing noise in the supply voltage. The part of the noise that is caused by switching of the internal logic load is core switching noise. The core logic switches at much higher speed than driver speed whereas the package inductance is less than the on-chip inductance in modern BGA packages. The core switching noise is currently gaining more attention for three-dimensional integrated circuits where on-chip inductance is much higher than the board and package inductance due to smaller board, and package. The switching noise of the driver is smaller than the core switching noise due to small driver size and reduced capacitance associated with short on-board wires for three-dimensional integrated circuits. The load increases with the addition of each die. The power distribution TSV pairs to supply each extra die also introduce additional parasitic. The core switching noise may propagate through substrate and consequently through interconnecting TSVs to different dies in heterogeneous integrated system. Core switching noise may lead to decreased device drive capability, increased gate delays, logic errors, and reduced noise margins. The actual behavior of the on-chip load is not well known in the beginning of the design cycle whereas altering the design during later stages is not cost effective. The size of a three-dimensional power distribution network may reach billions of nodes with the addition of dies in a vertical stack. The traditional tools may run out of time and memory during simulation of a three-dimensional power distribution network whereas, the CAD tools for the analysis of 3D power distribution network are in the process of evolution. Compact mathematical models for the estimation of core switching noise are necessary in order to overcome the power integrity challenges associated with the 3D power distribution network design. This thesis presents three different mathematical models to estimate core switching noise for 3D stacked power distribution networks. A time-domain-based mathematical model for the estimation of design parameters of a power distribution TSV pair is also proposed. Design guidelines for the estimation of optimum decoupling capacitance based on flat output impedance are also proposed for each stage of the vertical chain of power distribution TSV pairs. A mathematical model for tradeoff between TSV resistance and amount of decoupling capacitance on each DRAM die is proposed for a 3D-DRAM-Over-Logic system. The models are developed by following a three step approach: 1) design physical model, 2) convert it to equivalent electrical model, and 3) formulate the mathematical model based on the electrical model. The accuracy, speed and memory requirement of the proposed mathematical model is compared with equivalent Ansoft Nexxim models.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2012. , xxviii, 108 p.
Series
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 12:06
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-103566ISBN: 978-91-7501-519-4 (print)OAI: oai:DiVA.org:kth-103566DiVA: diva2:560517
Public defence
2012-11-07, Sal/Hal Sal E, Forum, KTH-ICT, Isafjordsgatan 39, Kista, 09:00 (English)
Opponent
Supervisors
Note

QC 20121015

Available from: 2012-10-15 Created: 2012-10-15 Last updated: 2012-10-15Bibliographically approved
List of papers
1. Peak-to-Peak Ground Noise on a Power Distribution TSV Pair as a Function of Rise Time in 3-D Stack of Dies Interconnected Through TSVs
Open this publication in new window or tab >>Peak-to-Peak Ground Noise on a Power Distribution TSV Pair as a Function of Rise Time in 3-D Stack of Dies Interconnected Through TSVs
2011 (English)In: IEEE Transactions on Components Packaging and Manufacturing Technology, ISSN 2156-3950, Vol. 1, no 2, 196-207 p.Article in journal (Refereed) Published
Abstract [en]

Supply grids of integrated chips are interconnected through through-silicon vias (TSVs) in modern design techniques to form a 3-D stack in vertical direction. The load on each chip is supplied through (power/ground) TSV pairs. Accurate estimation of power/ground noise on each TSV pair of a 3-D power distribution network is necessary for a robust power supply design. The worst case noise obtained with fast switching characteristics may not be significantly accurate. The behavior of power/ground noise as a function of rise time for an inductive power distribution TSV pair with decoupling capacitance, is investigated in this paper. An equivalent rise time corresponding to resonance is presented to accurately estimate the worst case power/ground noise in the time domain. In addition noise sensitivity to decoupling capacitance and TSV inductance is evaluated as a function of rise time. We also discuss noise accumulation as a result of worst case damping factor in this paper.

Keyword
Decoupling capacitance, ground noise, resonance, rise time, 3-D stack, target impedance, through-silicon vias (TSVs)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-37174 (URN)10.1109/TCPMT.2010.2099732 (DOI)000292779200006 ()2-s2.0-84866728950 (Scopus ID)
Available from: 2011-08-02 Created: 2011-08-02 Last updated: 2012-10-15Bibliographically approved
2. Modeling of peak-to-peak switching noise along a vertical chain of power distribution TSV pairs in a 3D stack of ICs interconnected through TSVs
Open this publication in new window or tab >>Modeling of peak-to-peak switching noise along a vertical chain of power distribution TSV pairs in a 3D stack of ICs interconnected through TSVs
2010 (English)In: 28th Norchip Conference, NORCHIP 2010, 2010, 5669473Conference paper, Published paper (Refereed)
Abstract [en]

On-chip power supply noise has become a bottleneck in 3D ICs as scaling of the supply network impedance has not been kept up with increasing device densities and operating currents with each technology node due to limited wire resources. In this paper we proposed an efficient and accurate model to estimate peak-to-peak switching noise, caused by simultaneous switching of logic loads along a vertical chain of power distribution TSV pairs in a 3D stack of ICs. The proposed model is quite accurate with only 2-3% difference from Ansoft Nexxim4.1 equivalent model. The proposed model is 3-4 times faster than Nexxim4.1 as well as consumes two times less memory as compared to Nexxim4.1equivalent model. We analyzed peak-to-peak switching noise along a vertical chain of power distribution TSV pairs by varying physical dimensions of TSVs and value of decoupling capacitance. We also thoroughly investigated the peak-to-peak noise sensitivity to TSV effective inductance and decoupling capacitance.

Keyword
3D stack of ICs, Power supply noise, Vertical chain
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-103505 (URN)10.1109/NORCHIP.2010.5669473 (DOI)2-s2.0-78751554093 (Scopus ID)
Conference
28th Norchip Conference, Tampere;15 November 2010 through16 November 2010, Finland
Note

QC 20121015

Available from: 2012-10-15 Created: 2012-10-15 Last updated: 2017-01-10Bibliographically approved
3. Modeling of peak-to-peak core switching noise, output impedance, and decoupling capacitance along a vertical chain of power distribution TSV pairs
Open this publication in new window or tab >>Modeling of peak-to-peak core switching noise, output impedance, and decoupling capacitance along a vertical chain of power distribution TSV pairs
2012 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 73, no 1, 311-328 p.Article in journal (Refereed) Published
Abstract [en]

In this article we propose an efficient and accurate model to estimate peak-to-peak core switching noise, caused by simultaneous switching of logic loads along a vertical chain of power distribution TSV pairs in a 3D stack of dies interconnected through TSVs. The proposed model is accurate with only a 2–3% difference in peak-to-peak core switching noise as compared to the Ansoft Nexxim4.1 equivalent model. The proposed model is 3–4 times faster than Ansoft Nexxim4.1 and uses two times less memory as compared to the Ansoft Nexxim4.1 equivalent model. In this article we also thoroughly establish design guidelines for almost flat output impedance magnitude at each stage of a vertical chain of power distribution TSV pairs to realize a resonance free scenario over a wide operating frequency range. We also establish decoupling capacitance design guidelines based on the optimum output impedance and critically damped supply voltage for the core logic for each stage of a vertical chain of power distribution TSV pairs.

Keyword
Core switching noise, 3D stack of dies, Vertical chain, Power distribution TSV pairs
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-103556 (URN)10.1007/s10470-011-9797-0 (DOI)000309130700032 ()2-s2.0-84866731975 (Scopus ID)
Funder
EU, FP7, Seventh Framework Programme, FP7-ICT-215030
Note

QC 20121015

Available from: 2012-10-15 Created: 2012-10-15 Last updated: 2017-12-07Bibliographically approved
4. Power Integrity Optimization of 3D Chips Stacked Through TSVs
Open this publication in new window or tab >>Power Integrity Optimization of 3D Chips Stacked Through TSVs
Show others...
2009 (English)In: ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS, NEW YORK: IEEE , 2009, 105-108 p.Conference paper, Published paper (Refereed)
Abstract [en]

On-chip power distribution network model for simultaneous switching of 3D ICs stacked through TSVs to choose TSV pattern, maximum number of chips in a stack and location of the decoupling capacitor for early design trade-offs.

Place, publisher, year, edition, pages
NEW YORK: IEEE, 2009
Keyword
Power integrity, Power distribution network, Peripheral TSVs
National Category
Chemical Engineering
Identifiers
urn:nbn:se:kth:diva-34393 (URN)000290737000027 ()2-s2.0-74549182688 (Scopus ID)978-1-4244-4448-9 (ISBN)
Conference
18th Conference on Electrical Performance of Electronic Packaging and Systems
Note
QC 20110607Available from: 2011-06-07 Created: 2011-06-07 Last updated: 2012-10-15Bibliographically approved
5. Power distribution TSVs induced core switching noise
Open this publication in new window or tab >>Power distribution TSVs induced core switching noise
Show others...
2011 (English)In: Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), 2010 IEEE, IEEE conference proceedings, 2011Conference paper, Published paper (Refereed)
Abstract [en]

Size of on-chip interconnects as well as the supply voltage is reducing with each technology node whereas the operating speed is increasing in modern VLSI design. Today, the package inductance and resistance has been reduced to such an extent that core switching noise caused by on-chip inductance and on-chip resistance is gaining importance as compared to I/O drivers switching noise. Both on-chip inductance and skin effect are prime players at frequencies of the order of GHz. The problem is further aggravated when chips are interconnected through TSVs to form a 3D integrated stack in order to achieve low form factor and high integration density. In this paper we analysed peak core switching noise in a 3D stack of integrated chips interconnected through power distribution TSV pairs, through our comprehensive mathematical model which has been proved to be quite accurate as compared to SPICE. We analysed the effect of number of chips in a 3D stack, rise time, decoupling capacitance, and skin effect on power distribution TSVs induced core switching noise in this paper.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2011
Keyword
3D stack, Core switching noise, Rise time, Skin effect
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-103557 (URN)10.1109/EDAPS.2010.5683008 (DOI)2-s2.0-79851475832 (Scopus ID)978-1-4244-9069-1 (ISBN)
Conference
Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), 2010 IEEE, Singapore
Note

QC 20121015

Available from: 2012-10-15 Created: 2012-10-15 Last updated: 2013-04-23Bibliographically approved
6. Fast Transient Simulation Algorithm for a 3D Power distribution Bus
Open this publication in new window or tab >>Fast Transient Simulation Algorithm for a 3D Power distribution Bus
Show others...
2010 (English)In: Proceedings of IEEE Asia Symposium on Quality Electronic Design, 2010, 343-350 p.Conference paper, Published paper (Refereed)
Abstract [en]

Extensive transient simulations for on-chip power delivery networks are required to analyze power delivery fluctuations caused by dynamic IR and Ldi/dt drops. Speed and memory has become a bottleneck for simulation of power distribution networks in modern VLSI design where clock frequency is of the order of GHz. The traditional SPICE based tools are very slow and consume a lot of memory during simulation. The problem is further aggravated for huge networks like power distribution network within a stack of ICs inter-connected through TSVs. This type of 3D power distribution network may contain billions of nodes at a time. In this paper we proposed a faster transient simulation algorithm using visual C++. First we reduce 3D power distribution bus containing n nodes to a two terminal 7 network. Then we solve this two terminal reduced network for voltages and currents. After this, we apply back solving algorithm to the network to solve it for each of the intermediate nodes using visual C++. The proposed algorithm is quite accurate with 1-2% error when compared with Ansoft Nexxim4.1. The proposed algorithm is several times faster than Ansoft Nexxim as well as consumes significantly less memory as compared to Nexxim.

Keyword
π Network, 3D power distribution network, Transient simulation, Vertical stack
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-103558 (URN)10.1109/ASQED.2010.5548313 (DOI)2-s2.0-77956542052 (Scopus ID)
Conference
2nd Asia Symposium on Quality Electronic Design, ASQED 2010; Penang; Malaysia; 3 August 2010 through 4 August 2010
Note

QC 20121015

Available from: 2012-10-15 Created: 2012-10-15 Last updated: 2017-04-12Bibliographically approved
7. Peak-to-peak Switching Noise and LC Resonance on a Power Distribution TSV Pair
Open this publication in new window or tab >>Peak-to-peak Switching Noise and LC Resonance on a Power Distribution TSV Pair
2010 (English)In: 2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010, Institute of Electrical and Electronics Engineers (IEEE), 2010, 173-176 p., 5642574Conference paper, Published paper (Refereed)
Abstract [en]

How peak-to-peak switching noise as well as the LC resonance term varies by varying different circuit parameters of a power distribution TSV pair (having decoupling capacitance and logic load), within a 3D stack of ICs interconnected through TSVs.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2010
Keyword
3D stack of ICs, LC resonance, Peak-to-peak noise
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-103559 (URN)10.1109/EPEPS.2010.5642574 (DOI)2-s2.0-78650935583 (Scopus ID)
Conference
2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010, Austin, TX, United States, 25 October 2010 through 27 October 2010
Note

QC 20121015

Available from: 2012-10-15 Created: 2012-10-15 Last updated: 2017-01-10Bibliographically approved
8. Decoupling capacitance for the power integrity of 3D-DRAM-over-logic system
Open this publication in new window or tab >>Decoupling capacitance for the power integrity of 3D-DRAM-over-logic system
2012 (English)In: IEEE 13th Electronics Packaging Technology Conference (EPTC), 2011, IEEE conference proceedings, 2012, 590-594 p.Conference paper, Published paper (Refereed)
Abstract [en]

The 3D-DRAM stacked over the processor is a vibrant technique in order to overcome the memory wall as well as the bandwidth wall problems. We considered a system with two DRAM dies over a single processor die. We assumed the decoupling capacitors to be placed on each DRAM die and connected to the power distribution TSV pairs, where the TSVs pass through the DRAM stack. In this paper we proposed a mathematical model for the optimum value of the decoupling capacitance on each DRAM die along with the optimum values of the effective resistance of the interconnecting power distribution TSV pairs in order to ensure the power integrity of the logic load during switching. The proposed model has a maximum of 1.1% error as compared to the Ansoft Nexxim4.1.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2012
Keyword
3D-DRAM, Decoupling capacitance, Power integrity
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-103560 (URN)10.1109/EPTC.2011.6184489 (DOI)2-s2.0-84860909009 (Scopus ID)978-1-4577-1981-3 (ISBN)
Conference
IEEE 13th Electronics Packaging Technology Conference (EPTC), 2011, Singapore
Note

QC 20121015

Available from: 2012-10-15 Created: 2012-10-15 Last updated: 2013-04-23Bibliographically approved
9. Switching Noise in 3D Power Distribution Networks: an Overview
Open this publication in new window or tab >>Switching Noise in 3D Power Distribution Networks: an Overview
2012 (English)In: VLSI  design / [ed] Esteban Tlelo-Cuautle, Sheldon Tan, Intech , 2012, 209-224 p.Chapter in book (Refereed)
Place, publisher, year, edition, pages
Intech, 2012
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-103561 (URN)978-953-307-884-7 (ISBN)
Note

QC 20121015

Available from: 2012-10-15 Created: 2012-10-15 Last updated: 2012-10-15Bibliographically approved

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