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Constraint-Based Register Allocation and Instruction Scheduling
SICS (Swedish Institute of Computer Science), Sweden.ORCID iD: 0000-0002-2806-7333
SICS (Swedish Institute of Computer Science), Sweden.
SICS (Swedish Institute of Computer Science), Sweden.
KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS. SICS (Swedish Institute of Computer Science), Sweden.ORCID iD: 0000-0002-6283-7004
2012 (English)In: Principles and Practice of Constraint Programming: 18th International Conference, CP 2012, Québec City, QC, Canada, October 8-12, 2012. Proceedings / [ed] Michela Milano, Springer, 2012, 750-766 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper introduces a constraint model and solving techniques for code generation in a compiler back-end. It contributes a new model for global register allocation that combines several advanced aspects: multiple register banks (subsuming spilling to memory), coalescing, and packing. The model is extended to include instruction scheduling and bundling. The paper introduces a decomposition scheme exploiting the underlying program structure and exhibiting robust behavior for functions with thousands of instructions. Evaluation shows that code quality is on par with LLVM, a state-of-the-art compiler infrastructure.

The paper makes important contributions to the applicability of constraint programming as well as compiler construction: essential concepts are unified in a high-level model that can be solved by readily available modern solvers. This is a significant step towards basing code generation entirely on a high-level model and by this facilitates the construction of correct, simple, flexible, robust, and high-quality code generators.

Place, publisher, year, edition, pages
Springer, 2012. 750-766 p.
Series
Lecture Notes in Computer Science, ISSN 0302-9743 ; 7514
Keyword [en]
Computer programming, Constraint theory, Flocculation, Network components
National Category
Computer Science Computer Systems
Identifiers
URN: urn:nbn:se:kth:diva-104554DOI: 10.1007/978-3-642-33558-7_54Scopus ID: 2-s2.0-84868266938ISBN: 978-3-642-33557-0 (print)ISBN: 978-3-642-33558-7 (print)OAI: oai:DiVA.org:kth-104554DiVA: diva2:565033
Conference
18th International Conference on Principles and Practice of Constraint Programming, CP 2012; Quebec City, QC; 8 October 2012 through 12 October 2012
Note

QC 20121212

Available from: 2012-11-05 Created: 2012-11-05 Last updated: 2016-04-21Bibliographically approved
In thesis
1. Integrated Register Allocation and Instruction Scheduling with Constraint Programming
Open this publication in new window or tab >>Integrated Register Allocation and Instruction Scheduling with Constraint Programming
2014 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

This dissertation proposes a combinatorial model, program representations, and constraint solving techniques for integrated register allocation and instruction scheduling in compiler back-ends. In contrast to traditional compilers based on heuristics, the proposed approach generates potentially optimal code by considering all trade-offs between interdependent decisions as a single optimization problem.

The combinatorial model is the first to handle a wide array of global register allocation subtasks, including spill code optimization, ultimate coalescing, register packing, and register bank assignment, as well as instruction scheduling for Very Long Instruction Word (VLIW) processors. The model is based on three novel, complementary program representations: Linear Static Single Assignment for global register allocation; copy extension for spilling, basic coalescing, and register bank assignment; and alternative temporaries for spill code optimization and ultimate coalescing. Solving techniques are proposed that exploit the program representation properties for scalability.

The model, program representations, and solving techniques are implemented in Unison, a code generator that delivers potentially optimal code while scaling to medium-size functions. Thorough experiments show that Unison: generates faster code (up to 41% with a mean improvement of 7%) than LLVM (a state-of-the-art compiler) for Hexagon (a challenging VLIW processor), generates code that is competitive with LLVM for MIPS32 (a simpler RISC processor), is robust across different benchmarks such as MediaBench and SPECint 2006, scales up to medium-size functions of up to 1000 instructions, and adapts easily to different optimization criteria.

The contributions of this dissertation are significant. They lead to a combinatorial approach for integrated register allocation and instruction scheduling that is, for the first time, practical (it robustly scales to medium-size functions) and effective (it yields better code than traditional heuristic approaches).

Place, publisher, year, edition, pages
Stockholm, Sweden: KTH Royal Institute of Technology, 2014. 48 p.
Series
TRITA-ICT-ECS AVH, ISSN 1653-6363 ; 14:13
National Category
Computer Science
Research subject
Computer Science
Identifiers
urn:nbn:se:kth:diva-154599 (URN)978-91-7595-311-3 (ISBN)
Presentation
2014-11-27, Sal A, Electrum, Kistagången 16, Kista, Stockholm, 14:00 (English)
Opponent
Supervisors
Note

QC 20141117

Available from: 2014-11-17 Created: 2014-10-24 Last updated: 2014-11-17Bibliographically approved

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Castañeda Lozano, RobertoSchulte, Christian

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