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Integration and Fabrication Techniques for 3D Micro- and Nanodevices
KTH, School of Electrical Engineering (EES), Micro and Nanosystems.ORCID iD: 0000-0003-3452-6361
2012 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The development of micro and nano-electromechanical systems (MEMS and NEMS) with entirely new or improved functionalities is typically based on novel or improved designs, materials and fabrication methods. However, today’s micro- and nano-fabrication is restrained by manufacturing paradigms that have been established by the integrated circuit (IC) industry over the past few decades. The exclusive use of IC manufacturing technologies leads to limited material choices, limited design flexibility and consequently to sub-optimal MEMS and NEMS devices. The work presented in this thesis breaks new ground with a multitude of novel approaches for the integration of non-standard materials that enable the fabrication of 3D micro and nanoelectromechanical systems. The objective of this thesis is to highlight methods that make use of non-standard materials with superior characteristics or methods that use standard materials and fabrication techniques in a novel context. The overall goal is to propose suitable and cost-efficient fabrication and integration methods, which can easily be made available to the industry.

The first part of the thesis deals with the integration of bulk wire materials. A novel approach for the integration of at least partly ferromagnetic bulk wire materials has been implemented for the fabrication of high aspect ratio through silicon vias. Standard wire bonding technology, a very mature back-end technology, has been adapted for yet another through silicon via fabrication method and applications including liquid and vacuum packaging as well as microactuators based on shape memory alloy wires. As this thesis reveals, wire bonding, as a versatile and highly efficient technology, can be utilized for applications far beyond traditional interconnections in electronics packaging.

The second part presents two approaches for the 3D heterogeneous integration based on layer transfer. Highly efficient monocrystalline silicon/ germanium is integrated on wafer-level for the fabrication of uncooled thermal image sensors and monolayer-graphene is integrated on chip-level for the use in diaphragm-based pressure sensors.

The last part introduces a novel additive fabrication method for layer-bylayer printing of 3D silicon micro- and nano-structures. This method combines existing technologies, including focused ion beam implantation and chemical vapor deposition of silicon, in order to establish a high-resolution fabrication process that is related to popular 3D printing techniques.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2012. , xv, 91 p.
Series
TRITA-EE, ISSN 1653-5146 ; 2013:001
Keyword [en]
Microelectromechanical systems, MEMS, Nanoelectromechanical systems, NEMS, silicon, wafer-level, chip-level, through silicon via, TSV, packaging, 3D packaging, vacuum packaging, liquid encapsulation, integration, heterogeneous integration, wafer bonding, microactuators, shape memory alloy, SMA, wire bonding, magnetic assembly, self-assembly, 3D, 3D printing, focused ion beam, FIB
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:kth:diva-107125ISBN: 978-91-7501-583-5 (print)OAI: oai:DiVA.org:kth-107125DiVA: diva2:574700
Public defence
2013-01-18, F3, Lindstedtsvägen 26, KTH, Stockholm, 10:00 (English)
Opponent
Supervisors
Note

QC 20121207

Available from: 2012-12-07 Created: 2012-12-06 Last updated: 2016-08-11Bibliographically approved
List of papers
1. Pressure sensors based on suspended graphene membranes
Open this publication in new window or tab >>Pressure sensors based on suspended graphene membranes
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2013 (English)In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 88, 89-94 p.Article in journal (Refereed) Published
Abstract [en]

A novel pressure sensor based on a suspended graphene membrane is proposed. The sensing mechanism is explained based on tight binding calculations of strain-induced changes in the band structure. A CMOS compatible fabrication process is proposed and used to fabricate prototypes. Electrical measurement data demonstrates the feasibility of the approach, which has the advantage of not requiring a separate strain gauge, i.e. the strain gauge is integral part of the pressure sensor membrane. Hence, graphene membrane based pressure sensors can in principle be scaled quite aggressively in size.

Keyword
Graphene, Sensor, Pressure, Nanotechnology, NEMS and Nanoelectromechanical System, Piezoresistive
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-106199 (URN)10.1016/j.sse.2013.04.019 (DOI)000323865300017 ()2-s2.0-84884979426 (Scopus ID)
Funder
EU, European Research Council, 277879 307311 228229
Note

QC 20131002. Updated from accepted to published.

Available from: 2012-11-29 Created: 2012-11-29 Last updated: 2017-12-07Bibliographically approved
2. Process considerations for layer-by-layer 3D patterning of silicon, using ion implantation, silicon deposition, and selective silicon etching
Open this publication in new window or tab >>Process considerations for layer-by-layer 3D patterning of silicon, using ion implantation, silicon deposition, and selective silicon etching
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2012 (English)In: Journal of Vacuum Science & Technology B, ISSN 1071-1023, E-ISSN 1520-8567, Vol. 30, no 6, 06FF05- p.Article in journal (Refereed) Published
Abstract [en]

The authors study suitable process parameters, and the resulting pattern formation, in additive layer-by-layer fabrication of arbitrarily shaped three-dimensional (3D) silicon (Si) micro- and nanostructures. The layer-by-layer fabrication process investigated is based on alternating steps of chemical vapor deposition of Si and local implantation of gallium ions by focused ion beam writing. In a final step, the defined 3D structures are formed by etching the Si in potassium hydroxide, where the ion implantation provides the etching selectivity.

Place, publisher, year, edition, pages
American Vacuum Society, 2012
Keyword
chemical vapour deposition, elemental semiconductors, etching, focused ion beam technology, gallium, ion implantation, nanofabrication, nanopatterning, nanostructured materials, semiconductor doping, semiconductor growth, silicon
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-105841 (URN)10.1116/1.4756947 (DOI)000311667300061 ()2-s2.0-84870358953 (Scopus ID)
Projects
M&Ms
Funder
EU, European Research Council, FP7-ERC-MM's 277879
Note

QC 20121129

Available from: 2012-11-29 Created: 2012-11-27 Last updated: 2017-12-07Bibliographically approved
3. Heterogeneous 3D integration of 17 mu m pitch Si/SiGe quantum well bolometer arrays for infrared imaging systems
Open this publication in new window or tab >>Heterogeneous 3D integration of 17 mu m pitch Si/SiGe quantum well bolometer arrays for infrared imaging systems
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2013 (English)In: Journal of Micromechanics and Microengineering, ISSN 0960-1317, E-ISSN 1361-6439, Vol. 23, no 4, 045017- p.Article in journal (Refereed) Published
Abstract [en]

This paper reports on the realization of 17 mu m x 17 mu m pitch bolometer arrays for uncooled infrared imagers. Microbolometer arrays have been available in primarily defense applications since the mid-1980s and are typically based on deposited thin films on top of CMOS wafers that are surface-machined into sensor pixels. This paper instead focuses on the heterogeneous integration of monocrystalline Si/SiGe quantum-well-based thermistor material in a CMOS-compliant process using adhesive wafer bonding. The high-quality monocrystalline thermistor material opens up for potentially lower noise compared to commercially available uncooled microbolometer arrays together with a competitive temperature coefficient of resistance (TCR). Characterized bolometers had a TCR of -2.9% K-1 in vacuum, measured thermal conductances around 5 x 10(-8) WK-1 and thermal time constants between 4.9 and 8.5 ms, depending on the design. Complications in the fabrication of stress-free bolometer legs and low-noise contacts are discussed and analyzed.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-106201 (URN)10.1088/0960-1317/23/4/045017 (DOI)000316299900018 ()2-s2.0-84878081474 (Scopus ID)
Note

QC 20130422. Updated from submitted to published.

Available from: 2012-11-29 Created: 2012-11-29 Last updated: 2017-12-07Bibliographically approved
4. Very Large Scale Heterogeneous Integration (VLSHI) and Wafer-Level Vacuum Packaging for Infrared Bolometer Focal Plane Arrays
Open this publication in new window or tab >>Very Large Scale Heterogeneous Integration (VLSHI) and Wafer-Level Vacuum Packaging for Infrared Bolometer Focal Plane Arrays
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2013 (English)In: Infrared physics & technology, ISSN 1350-4495, E-ISSN 1879-0275, Vol. 60, 251-259 p.Article in journal (Refereed) Published
Abstract [en]

Imaging in the long wavelength infrared (LWIR) range from 8 to 14 μm is an extremely useful tool for non-contact measurement and imaging of temperature in many industrial, automotive and security applications. However, the cost of the infrared (IR) imaging components has to be significantly reduced to make IR imaging a viable technology for many cost-sensitive applications. This paper demonstrates new and improved fabrication and packaging technologies for next-generation IR imaging detectors based on uncooled IR bolometer focal plane arrays. The proposed technologies include very large scale heterogeneous integration for combining high-performance, SiGe quantum-well bolometers with electronic integrated read-out circuits and CMOS compatible wafer-level vacuum packing. The fabrication and characterization of bolometers with a pitch of 25 μm × 25 μm that are arranged on read-out-wafers in arrays with 320 × 240 pixels are presented. The bolometers contain a multi-layer quantum well SiGe thermistor with a temperature coefficient of resistance of −3.0%/K. The proposed CMOS compatible wafer-level vacuum packaging technology uses Cu–Sn solid–liquid interdiffusion (SLID) bonding. The presented technologies are suitable for implementation in cost-efficient fabless business models with the potential to bring about the cost reduction needed to enable low-cost IR imaging products for industrial, security and automotive applications.

Keyword
Very large scale heterogeneous integration, Thermal imaging, MEMS, Bolometer, IR
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-106202 (URN)10.1016/j.infrared.2013.05.006 (DOI)000324004900034 ()2-s2.0-84879956633 (Scopus ID)
Note

QC 20131003 Updated from Submitted to Published

Available from: 2012-11-29 Created: 2012-11-29 Last updated: 2017-12-07Bibliographically approved
5. Wire-bonded through-silicon vias with low capacitive substrate coupling
Open this publication in new window or tab >>Wire-bonded through-silicon vias with low capacitive substrate coupling
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2011 (English)In: Journal of Micromechanics and Microengineering, ISSN 0960-1317, E-ISSN 1361-6439, Vol. 21, no 8, 085035- p.Article in journal (Refereed) Published
Abstract [en]

Three-dimensional integration of electronics and/or MEMS-based transducers is an emerging technology that vertically interconnects stacked dies with through-silicon vias (TSVs). They enable the realization of circuits with shorter signal path lengths, smaller packages and lower parasitic capacitances, which results in higher performance and lower costs. This paper presents a novel technique for fabricating TSVs from bonded gold wires. The wires are embedded in a polymer, which acts both as an electrical insulator, resulting in low capacitive coupling toward the substrate and as a buffer for thermo-mechanical stress.

Place, publisher, year, edition, pages
IOP Science, 2011
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-37546 (URN)10.1088/0960-1317/21/8/085035 (DOI)000293163700035 ()2-s2.0-79961219588 (Scopus ID)
Note
QC 20110816Available from: 2011-11-08 Created: 2011-08-15 Last updated: 2017-12-08Bibliographically approved
6. Wire-bonder-assisted integration of non-bondable SMA wires into MEMS substrates
Open this publication in new window or tab >>Wire-bonder-assisted integration of non-bondable SMA wires into MEMS substrates
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2012 (English)In: Journal of Micromechanics and Microengineering, ISSN 0960-1317, E-ISSN 1361-6439, Vol. 22, no 5, 055025- p.Article in journal (Refereed) Published
Abstract [en]

This paper reports on a novel technique for the integration of NiTi shape memory alloy wires and other non-bondable wire materials into silicon-based microelectromechanical system structures using a standard wire-bonding tool. The efficient placement and alignment functions of the wire-bonding tool are used to mechanically attach the wire to deep-etched silicon anchoring and clamping structures. This approach enables a reliable and accurate integration of wire materials that cannot be wire bonded by traditional means.

Place, publisher, year, edition, pages
Institute of Physics Publishing (IOPP), 2012
Keyword
Bonding, Electromechanical devices, Integration, MEMS
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-90858 (URN)10.1088/0960-1317/22/5/055025 (DOI)000303197000025 ()2-s2.0-84860433128 (Scopus ID)
Funder
EU, European Research Council, 267528 277879
Note
QC 20120528Available from: 2012-04-20 Created: 2012-03-01 Last updated: 2017-12-07Bibliographically approved
7. Very high aspect ratio through-silicon vias (TSVs) fabricated using automated magnetic assembly of nickel wires
Open this publication in new window or tab >>Very high aspect ratio through-silicon vias (TSVs) fabricated using automated magnetic assembly of nickel wires
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2012 (English)In: Journal of Micromechanics and Microengineering, ISSN 0960-1317, E-ISSN 1361-6439, Vol. 22, no 10, 105001- p.Article in journal (Refereed) Published
Abstract [en]

Through-silicon via (TSV) technology enables 3D-integrated devices with higher performance and lower cost as compared to 2D-integrated systems. This is mainly due to smaller dimensions of the package and shorter internal signal lengths with lower capacitive, resistive and inductive parasitics. This paper presents a novel low-cost fabrication technique for metal-filled TSVs with very high aspect ratios (>20). Nickel wires are placed in via holes of a silicon wafer by an automated magnetic assembly process and are used as a conductive path of the TSV. This metal filling technique enables the reliable fabrication of through-wafer vias with very high aspect ratios and potentially eliminates characteristic cost drivers in the TSV production such as advanced metallization processes, wafer thinning and general issues associated with thin-wafer handling.

Place, publisher, year, edition, pages
Institute of Physics (IOP), 2012
Keyword
Electronics packaging, Silicon wafers, Wire
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-101062 (URN)10.1088/0960-1317/22/10/105001 (DOI)000309219500001 ()2-s2.0-84866321637 (Scopus ID)
Funder
EU, European Research Council, 277879
Note

QC 20120827

Available from: 2012-08-27 Created: 2012-08-22 Last updated: 2017-12-07Bibliographically approved
8. 3D Free-Form Patterning of Silicon by Ion Implantation, Silicon Deposition, and Selective Silicon Etching
Open this publication in new window or tab >>3D Free-Form Patterning of Silicon by Ion Implantation, Silicon Deposition, and Selective Silicon Etching
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2012 (English)In: Advanced Functional Materials, ISSN 1616-301X, E-ISSN 1616-3028, Vol. 22, no 19, 4004-4008 p.Article in journal (Refereed) Published
Abstract [en]

A method for additive layer-by-layer fabrication of arbitrarily shaped 3D silicon micro- and nanostructures is reported. The fabrication is based on alternating steps of chemical vapor deposition of silicon and local implantation of gallium ions by focused ion beam (FIB) writing. In a final step, the defined 3D structures are formed by etching the silicon in potassium hydroxide (KOH), in which the local ion implantation provides the etching selectivity. The method is demonstrated by fabricating 3D structures made of two and three silicon layers, including suspended beams that are 40 nm thick, 500 nm wide, and 4 μm long, and patterned lines that are 33 nm wide.

Place, publisher, year, edition, pages
Wiley-VCH Verlagsgesellschaft, 2012
Keyword
microelectromechanical systems, nanostructures, additive layer-by-layer fabrication, 3D silicon patterning, focused ion beam (FIB) implantation
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-97985 (URN)10.1002/adfm.201200845 (DOI)000309404000004 ()2-s2.0-84867061585 (Scopus ID)
Funder
EU, European Research Council, 277879 MM's
Note

QC 20120618

Available from: 2012-06-18 Created: 2012-06-18 Last updated: 2017-12-07Bibliographically approved
9. High-Aspect-Ratio Through Silicon Vias for High-Frequency Application Fabricated by Magnetic Assembly of Gold-Coated Nickel Wires
Open this publication in new window or tab >>High-Aspect-Ratio Through Silicon Vias for High-Frequency Application Fabricated by Magnetic Assembly of Gold-Coated Nickel Wires
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2015 (English)In: IEEE Transactions on Components, Packaging, and Manufacturing Technology, ISSN 2156-3950, E-ISSN 2156-3985, Vol. 5, no 1, 21-27 p.Article in journal (Refereed) Published
Abstract [en]

In this paper, we demonstrate a novel manufacturing technology for high-aspect-ratio vertical interconnects for high-frequency applications. This novel approach is based on magnetic self-assembly of prefabricated nickel wires that are subsequently insulated with a thermosetting polymer. The high-frequency performance of the through silicon vias (TSVs) is enhanced by depositing a gold layer on the outer surface of the nickel wires and by reducing capacitive parasitics through a low-k polymer liner. As compared with conventional TSV designs, this novel concept offers a more compact design and a simpler, potentially more cost-effective manufacturing process. Moreover, this fabrication concept is very versatile and adaptable to many different applications, such as interposer, micro electromechanical systems, or millimeter wave applications. For evaluation purposes, coplanar waveguides with incorporated TSV interconnections were fabricated and characterized. The experimental results reveal a high bandwidth from dc to 86 GHz and an insertion loss of <0.53 dB per single TSV interconnection for frequencies up to 75 GHz.

Place, publisher, year, edition, pages
IEEE Press, 2015
Keyword
RF signal transmission, skin effect, through silicon via (TSV), vertical interconnection, wafer scale integration
National Category
Materials Engineering
Identifiers
urn:nbn:se:kth:diva-160401 (URN)10.1109/TCPMT.2014.2369236 (DOI)000348123200004 ()2-s2.0-84921411485 (Scopus ID)
Funder
Swedish Research Council, 277879
Note

QC 20150224

Available from: 2015-02-24 Created: 2015-02-19 Last updated: 2017-12-04Bibliographically approved
10. Wafer-Level Vacuum Sealing by Coining of Wire Bonded Gold Bumps
Open this publication in new window or tab >>Wafer-Level Vacuum Sealing by Coining of Wire Bonded Gold Bumps
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2013 (English)In: Journal of microelectromechanical systems, ISSN 1057-7157, E-ISSN 1941-0158, Vol. 22, no 6, 1347-1353 p.Article in journal (Refereed) Published
Abstract [en]

This paper reports on the investigation of a novel room-temperature vacuum sealing method based on compressing wire bonded gold bumps which are placed to partially overlap the access ports into the cavity. The bump compression, which is done under vacuum, causes a material flow into the access ports, thereby hermetically sealing a vacuum inside the cavities. The sealed cavity pressure was measured by residual gas analysis to 8x10(-4) mbar two weeks after sealing. The residual gas content was found to be mainly argon, which indicates the source as outgassing inside the cavity and no measurable external leak. The seals are found to be mechanically robust and easily implemented by the use of standard commercial tools and processes.

Keyword
Vacuum, packaging, MEMS, wire bonding, sealing, hermetic
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-106203 (URN)10.1109/JMEMS.2013.2262594 (DOI)000328047300012 ()2-s2.0-84897679362 (Scopus ID)
Funder
EU, European Research Council, 267528
Note

QC 20140108. Updated from submitted to published.

Available from: 2012-11-29 Created: 2012-11-29 Last updated: 2017-12-07Bibliographically approved
11. Hermetic integration of liquids using high-speed stud bump bonding for cavity sealing at the wafer level
Open this publication in new window or tab >>Hermetic integration of liquids using high-speed stud bump bonding for cavity sealing at the wafer level
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2012 (English)In: Journal of Micromechanics and Microengineering, ISSN 0960-1317, E-ISSN 1361-6439, Vol. 22, no 4, 045021- p.Article in journal (Refereed) Published
Abstract [en]

This paper reports a novel room-temperature hermetic liquid sealing process where the access ports of liquid-filled cavities are sealed with wire-bonded stud bumps. This process enables liquids to be integrated at the fabrication stage. Evaluation cavities were manufactured and used to investigate the mechanical and hermetic properties of the seals. Measurements on the successfully sealed structures show a helium leak rate of better than 10 (10) mbarL s (1), in addition to a zero liquid loss over two months during storage near boiling temperature. The bond strength of the plugs was similar to standard wire bonds on flat surfaces.

National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-95264 (URN)10.1088/0960-1317/22/4/045021 (DOI)000303196900021 ()
Funder
EU, European Research Council, 267528
Note
QC 20120521Available from: 2012-05-21 Created: 2012-05-21 Last updated: 2017-12-07Bibliographically approved

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