An Improved Hardware Implementation of the Grain-128a Stream Cipher
2012 (English)In: Lecture Notes in Computer Science / [ed] Springer-Verlag, 2012, 278-292 p.Conference paper (Refereed)
We study efficient high-throughput hardware implementations of the Grain-128a family of stream ciphers. To increase the throughput compared to the standard design, we apply five different techniques in combination: isolation of the authentication section, Fibonacci-to-Galois transformation of the feedback shift registers, multi-frequency implementation, simplification of the pre-outputs functions and internal pipelining. The combined effect of all these techniques enables an average 56% higher keystream generation throughput among all the ciphers, at the expense of an average 8% area penalty, an average 4% power overhead and a 21% slower keystream initialization phase. An alternative combination of techniques allows an average 23% throughput improvement in all phases.
Place, publisher, year, edition, pages
2012. 278-292 p.
, Lecture notes in computer science, 7839
Computer Systems Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-107696DOI: 10.1007/978-3-642-37682-5_20ScopusID: 2-s2.0-84875971567OAI: oai:DiVA.org:kth-107696DiVA: diva2:577679
International Conference on Information Security and Cryptology (ICISC)
QC 201312122012-12-162012-12-162013-12-12Bibliographically approved