Energy-Aware CGRAs using Dynamically Re-configurable isolation Cells
2013 (English)Conference paper, Presentation (Refereed)
This paper presents a self adaptive architectureto enhance the energy efﬁciency of coarse-grained reconﬁgurablearchitectures (CGRAs). Today, platforms host multipleapplications, with arbitrary inter-application communication andconcurrency patterns. Each application itself can have multipleversions (implementations with different degree of parallelism)and the optimal version can only be determined at runtime. Forsuch scenarios, traditional worst case designs and compile timemapping decisions are neither optimal nor desirable. Existingsolutions to this problem employ costly dedicated hardware toconﬁgure the operating point at runtime (using DVFS). As analternative to dedicated hardware, we propose exploiting thereconﬁguration features of modern CGRAs. Our solution relieson dynamically reconﬁgurable isolation cells (DRICs) and autonomousparallelism, voltage, and frequency selection algorithm(APVFS). The DRICs reduce the overheads of DVFS circuitryby conﬁguring the existing resources as isolation cells. APVFSensures high efﬁciency by dynamically selecting the parallelism,voltage and frequency trio, which consumes minimum powerto meet the deadlines on available resources. Simulation resultsusing representative applications (Matrix multiplication, FIR,and FFT) showed up to 23% and 51% reduction in powerand energy, respectively, compared to traditional DVFS designs.Synthesis results have conﬁrmed signiﬁcant reduction in areaoverheads compared to state of the art DVFS methods.
Place, publisher, year, edition, pages
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-109404OAI: oai:DiVA.org:kth-109404DiVA: diva2:581848
International Symposium for Quality and Electronic Design (ISQED)
QC 201306262013-01-022013-01-022015-03-03Bibliographically approved