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Three-phase time-aware energy minimization with DVFS and unrolling for Chip Multiprocessors
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2012 (English)In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 58, no 10, 439-445 p.Article in journal (Refereed) Published
Abstract [en]

Energy consumption has been one of the most critical issues in the Chip Multiprocessor (CMP). Using the Dynamic Voltage and Frequency Scaling (DVFS), a CMP system can achieve a balance between the performance and the energy-efficiency. In this paper, we propose a three-phase discrete DVFS algorithm for a CMP system dedicated to applications where the period of the applications' task graph is smaller than the deadline of tasks. In these applications, multiple task graphs are unrolled and then concatenated together to form a new task graph. The proposed DVFS algorithm is applied to the newly formed task graph to stretch tasks' execution time, lower operating frequencies of processors and achieve the system power efficiency. Experimental results show that the proposed algorithm reduces the energy dissipation by 25% on average, compared to previous DVFS approaches.

Place, publisher, year, edition, pages
2012. Vol. 58, no 10, 439-445 p.
Keyword [en]
Real-time, CMP, Energy, DVFS, Task graph, Unrolling
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:kth:diva-109563DOI: 10.1016/j.sysarc.2012.07.001ISI: 000312175100005Scopus ID: 2-s2.0-84867901986OAI: oai:DiVA.org:kth-109563DiVA: diva2:583436
Note

QC 20130108

Available from: 2013-01-08 Created: 2013-01-08 Last updated: 2017-12-06Bibliographically approved

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Lu, Zhonghai

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