Low Power Instruction Fetch using Profiled Variable Length Instructions
2003 (English)Conference paper (Refereed)
Computer system performance depends on high access rate and low miss rate in the instruction cache, which also affects energy consumed by fetching instructions. Simulation of a small computer typical for embedded systems show that up to 20% of the overall processor energy is consumed in the instruction fetch path and as much as 23% of the execution time is spent on instruction fetch. One way to increase the instruction memory bandwidth is to fetch more instructions each access without increasing the bus width. We propose an extension to a RISC ISA, with variable length instructions, yielding higher information density without compromising programmability. Based on profiling of dynamic instruction usage and argument locality of a set of SPEC CPU2000 applications, we present a scheme using 8- 16- and 24-bit instructions accompanied by lookup tables inside the processor. Our scheme yields a 20-30% reduction in static memory usage, and experiments show that up to 60% of all executed instructions consist of short instructions. The overall energy savings are up to 15% for the entire data path and memory system, and up to 20% in the instruction fetch path.
Place, publisher, year, edition, pages
IdentifiersURN: urn:nbn:se:kth:diva-109678OAI: oai:DiVA.org:kth-109678DiVA: diva2:584886
IEEE International SoC Conference
NR 201408052013-01-092013-01-082013-01-09Bibliographically approved