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Scalable directory architecture for distributed shared memory chip multiprocessors
KTH, School of Information and Communication Technology (ICT), Communication: Services and Infrastucture (Closed 20120101), Software and Computer Systems, SCS (Closed 20120101).
KTH, School of Information and Communication Technology (ICT), Communication: Services and Infrastucture (Closed 20120101), Software and Computer Systems, SCS (Closed 20120101). (Kista Multicore Center)ORCID iD: 0000-0002-9637-2065
2008 (English)In: Proceedings of the 1st Swedish Workshop on Multi-core Computing, 2008, 73-81 p.Conference paper, Published paper (Refereed)
Abstract [en]

Traditional Directory-based cache coherence protocol is far from optimal for large-scale cache coherent shared memory multiprocessors due to the increasing latency to access directories stored in DRAM memory. Instead of keeping directories in main memory, we consider distributing the directory together with L2 cache across all nodes on a Chip Multiprocessor. Each node contains a processing unit, a private L1 cache, a slice of L2 cache, memory controller and a router. Both L2 cache and memories are distributed shared and interleaved by a subset of memory address bits. All nodes are interconnected through a low latency two dimensional Mesh network.

Directory, as a split component as L2 cache, only stores sharing information for blocks while L2 cache only stores data blocks exclusive with L1 cache. Shared L2 cache can increase total effective cache capacity on chip, but also increase the miss latency when data is on a remote node. Being different from Directory Cache structure, our proposal totally removes the directory from memory which saves memory space and reduces access latency. Compared to L2 cache which combines directory information internally, our split L2 cache structure saves over 88% cache space while having achieved similar performance.

Place, publisher, year, edition, pages
2008. 73-81 p.
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:kth:diva-109680OAI: oai:DiVA.org:kth-109680DiVA: diva2:584892
Conference
1st Swedish Workshop on Multi-core Computing
Note

QC 20130604

Available from: 2013-01-09 Created: 2013-01-08 Last updated: 2013-06-04Bibliographically approved

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Brorsson, Mats

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CiteExportLink to record
Permanent link

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Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
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