An Implementation of Cache-Coherence for the Nios II ™ Soft-core processor
2009 (English)Conference paper (Refereed)
Soft-core programmable processors mapped onto fieldprogrammable gate arrays (FPGA) can be considered as equivalents to a microcontroller. They combine central processing units (CPUs), caches, memories, and peripherals on a single chip. Soft-cores processors represent an increasingly common embedded software implementation option. Modern FPGA soft-cores are parameterized to support application-specific customization. However, these softcore processors are designed to be used in uniprocessor system, not for multiprocessor system. This project describes an implementation to solve the cache coherency problem in an ALTERA Nios II soft-core multiprocessor system.
Place, publisher, year, edition, pages
IdentifiersURN: urn:nbn:se:kth:diva-109653OAI: oai:DiVA.org:kth-109653DiVA: diva2:584904
2nd Swedish Workshop on Multi-core Computing
QC 201306042013-01-092013-01-082015-07-16Bibliographically approved