A model for parallel simulation of distributed shared memory
1996 (English)Conference paper (Refereed)
We present an execution model for parallel simulation of a distributed shared memory architecture. The model captures the processor-memory interaction and abstracts the memory subsystem. Using this model we show how parallel, on-line, partially-ordered memory traces can be correctly predicted without interacting with the memory subsystem. We also outline a parallel optimistic memory simulator that uses these traces, finds a global order among all events, and returns correct data and timing to each processor. A first evaluation of the amount of concurrency that our model can extract for an ideal multiprocessor shows that processors may execute relatively long instruction sequences without violating the causality constraints. However parallel simulation efficiency is highly dependent on the memory consistency model and the application characteristics.
Place, publisher, year, edition, pages
1996. 179-84 p.
IdentifiersURN: urn:nbn:se:kth:diva-109655OAI: oai:DiVA.org:kth-109655DiVA: diva2:584907
Proceedings of MASCOTS ‘96 - 4th International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems
NR 201408052013-01-092013-01-082013-01-09Bibliographically approved