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Modelling accesses to stationary data in a shared memory multiprocessor
Lund university.ORCID iD: 0000-0002-9637-2065
Lund university.
1994 (English)Conference paper, Published paper (Refereed)
Abstract [en]

Cache misses due to coherence and directory maintenance is a major reason for poor performance in shared memory multiprocessors. We show that the relationship between a particular access pattern and cache miss ratios for a class of directory-based, write-invalidate cache coherence protocols can be characterised in a small set of parameters. In order to do this, a reference generator has been designed that, based on parameters automatically extracted from a program, can artificially generate a reference stream that results in the same cold, coherence and directory replacement miss ratios as an execution of the program.

Place, publisher, year, edition, pages
1994. 802-7 p.
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:kth:diva-109673OAI: oai:DiVA.org:kth-109673DiVA: diva2:584925
Conference
Proceedings of 1994 7th International Conference on Parallel and Distributed Computing Systems
Note
NR 20140805Available from: 2013-01-09 Created: 2013-01-08 Last updated: 2013-01-09Bibliographically approved

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http://www.imit.kth.se/~matsbror/papers/brorsson_pdcs94.pdf

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Brorsson, Mats

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CiteExportLink to record
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