Modelling accesses to stationary data in a shared memory multiprocessor
1994 (English)Conference paper (Refereed)
Cache misses due to coherence and directory maintenance is a major reason for poor performance in shared memory multiprocessors. We show that the relationship between a particular access pattern and cache miss ratios for a class of directory-based, write-invalidate cache coherence protocols can be characterised in a small set of parameters. In order to do this, a reference generator has been designed that, based on parameters automatically extracted from a program, can artificially generate a reference stream that results in the same cold, coherence and directory replacement miss ratios as an execution of the program.
Place, publisher, year, edition, pages
1994. 802-7 p.
IdentifiersURN: urn:nbn:se:kth:diva-109673OAI: oai:DiVA.org:kth-109673DiVA: diva2:584925
Proceedings of 1994 7th International Conference on Parallel and Distributed Computing Systems
NR 201408052013-01-092013-01-082013-01-09Bibliographically approved