Integrating virtual platforms into a heterogeneous MoC-based modeling framework
2012 (English)In: Proceedings of Forum on Specification and Design Languages (FDL) 2012, IEEE conference proceedings, 2012, 143-150 p.Conference paper (Refereed)
In order to handle the increasing complexity of embedded systems, design methodologies must take into account important aspects, such as abstraction, IP-reuse and heterogeneity. System design often starts in a high abstraction level, by developing a virtual platform (VP), which is typically composed of TLM models. TLM has become very popular in the modeling of bus-based systems and currently there is an increasing availability of libraries that provide TLM IPs. Heterogeneity can be naturally captured in a framework supporting different Models of Computation (MoCs). We introduce a novel approach for integrating TLM IPs/VPs into a MoC-based modeling framework, allowing them to co-simulate heterogeneous systems. This approach allows to raise the abstraction level, enabling a more careful design space exploration before selecting a proper VP. We exemplify the potential of our approach with a case study in which a VP with a processor generated by ArchC communicates with a continuous-time model.
Place, publisher, year, edition, pages
IEEE conference proceedings, 2012. 143-150 p.
Adaptation models, Computational modeling, Protocols, Semantics, Software, Time domain analysis, Time varying systems, data structures, electronic design automation, embedded systems, logic circuits, system buses, virtual machines
IdentifiersURN: urn:nbn:se:kth:diva-104556ScopusID: 2-s2.0-84871091664ISBN: 978-1-4673-1240-0OAI: oai:DiVA.org:kth-104556DiVA: diva2:586223
Forum on Specification and Design Languages (FDL) 2012
QC 201301142013-01-112012-11-052013-01-14Bibliographically approved