A greedy heuristic approximation scheduling algorithm for 3d multicore processors
2012 (English)In: Euro-Par 2011: Parallel Processing Workshops, 2012, 281-291 p.Conference paper (Refereed)
In this paper, we propose a greedy heuristic approximation scheduling algorithm for future multicore processors. It is expected that hundreds of cores will be integrated on a single chip, known as a Chip Multiprocessor (CMP). To reduce on-chip communication delay, 3D integration with Through Silicon Vias (TSVs) is introduced to replace the 2D counterpart. Multiple functional layers can be stacked in a 3D CMP. However, operating system process scheduling, one of the most important design issues for CMP systems, has not been well addressed for such a system. We define a model for future 3D CMPs, based on which a scheduling algorithm is proposed to reduce cache access latencies and the delay of inter process communications (IPC). We explore different scheduling possibilities and discuss the advantages and disadvantages of our algorithm. We present benchmark results using a cycle accurate full system simulator based on realistic workloads. Experiments show that under two workloads, the execution times of our scheduling in two configurations (2 and 4 threads) are reduced by 15.58% and 8.13% respectively, compared with the other schedulings. Our study provides a guideline for designing scheduling algorithms for 3D multicore processors.
Place, publisher, year, edition, pages
2012. 281-291 p.
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-111521DOI: 10.1007/978-3-642-29737-3_32OAI: oai:DiVA.org:kth-111521DiVA: diva2:586750
Euro-Par 2011: Parallel Processing Workshops
QC 201305232013-01-122013-01-122013-05-23Bibliographically approved