Exploration of heuristic scheduling algorithms for 3D multicore processors
2012 (English)In: Proceedings of the 15th International Workshop on Software and Compilers for Embedded Systems, 2012, 22-31 p.Conference paper (Refereed)
In this paper, we explore heuristic scheduling algorithms for future multicore processors. It is expected that hundreds or even thousands of cores will be integrated on a single chip, known as a Chip Multiprocessor (CMP). To reduce on-chip communication delay and improve efficiency, three-dimensional (3D) integration with Through Silicon Vias (TSVs) is introduced to replace the traditional two-dimensional (2D) implementation. Multiple functional layers can be stacked in 3D CMPs. However, operating system process scheduling has not been well addressed for such systems. We define a model for 3D CMPs, and propose a heuristic scheduling algorithm which aims to reduce cache access latencies and the delay of inter process communication. We explore different scheduling methods and discuss the advantages and disadvantages of our algorithm. Experimental results show that under three different workloads, the execution times of our scheduling method in two configurations are reduced by 14.5% and 5.86% respectively, compared with the other scheduling methods. Two scheduling methods from different heuristics for 8-thread tasks are also compared. This research provides a guideline for designing scheduling algorithms for future 3D CMPs.
Place, publisher, year, edition, pages
2012. 22-31 p.
heuristic methods, multicore, scheduling, three-dimensional integrated circuit, through silicon via
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-111519DOI: 10.1145/2236576.2236579ScopusID: 2-s2.0-84863500914OAI: oai:DiVA.org:kth-111519DiVA: diva2:586756
15th International Workshop on Software and Compilers for Embedded Systems
QC 201305232013-01-122013-01-122013-05-23Bibliographically approved