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An Optimized Network-on-Chip Design for Data Parallel FFT
Turku Centre for Computer Science (TUCS).
Turku Centre for Computer Science (TUCS).
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
2012 (English)In: Procedia Engineering, ISSN 1877-7058, E-ISSN 1877-7058, Vol. 30, 311-318 p.Article in journal (Refereed) Published
Abstract [en]

In this paper, we propose an optimized Network-on-Chip (NoC) design for data parallel FFT applications. NoC based architecture is proposed for future multicore processors due to its scalability. FFT is widely used in digital systems. The implementation of FFT on conventional architectures have been studied. However, the evaluation of data parallel FFT in a NoC platform has not been well addressed. We analyse data parallel FFT in terms of traffic patterns and propose an optimized NoC design. Experiments show that, the execution time of our optimized design is 12.13% faster than the original

Place, publisher, year, edition, pages
2012. Vol. 30, 311-318 p.
Keyword [en]
FFT, Network-on-Chip, Data Parallel, Multicore, Optimization
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-111520DOI: 10.1016/j.proeng.2012.01.866ISI: 000314170600040OAI: oai:DiVA.org:kth-111520DiVA: diva2:586757
Note

QC 20130503

Available from: 2013-01-12 Created: 2013-01-12 Last updated: 2017-12-06Bibliographically approved

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