Change search
ReferencesLink to record
Permanent link

Direct link
Design and management of high-performance, reliable and thermal-aware 3D networks-on-chip
University of Turku.
University of Turku.
University of Turku.
University of Turku.
Show others and affiliations
2012 (English)In: IET Circuits, Devices & Systems, ISSN 1751-8598, E-ISSN 1751-8598, Vol. 6, no 5, 308-321 p.Article in journal (Refereed) Published
Abstract [en]

Increasing the number of cores over a 2D plane is not efficient in hyper-core systems due to long interconnects. As a viable alternative over the 2D planar chip, 3D integrated technology offers greater device integration and shorter interlayer interconnects. 3D networks-on-chip (NoC)-bus hybrid mesh architecture, which is a hybrid between packet-switched network and a bus, was proposed to take advantage of the intrinsic attributes of 3D ICs. Even though this architecture was proposed as a feasible one to provide both performance and area benefits, the challenges of combining both media (NoC and bus) to design 3D NoCs have not been addressed. In this study, an efficient 3D NoC architecture is proposed to optimise performance, power consumption and reliability of 3D NoC-bus hybrid mesh system. The mechanism benefits from a congestion-aware and bus failure tolerant routing algorithm called 'AdaptiveZ' for vertical communication. In addition, the authors propose thermal-aware scheduling strategy in order to mitigate temperature by herding most of the switching activity closer to the heatsink. To estimate the efficiency of the proposed architecture, the system has been simulated using uniform, hotspot 10% and negative exponential distribution traffic patterns. In addition, a videoconference encoder has been used as a real application for system analysis. Compared with a typical stacked mesh 3D NoC, our extensive simulations demonstrate significant power, performance and peak temperature improvements.

Place, publisher, year, edition, pages
2012. Vol. 6, no 5, 308-321 p.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
URN: urn:nbn:se:kth:diva-111512DOI: 10.1049/iet-cds.2011.0349ISI: 000310458700006OAI: diva2:586758

QC 20130116

Available from: 2013-01-12 Created: 2013-01-12 Last updated: 2015-07-29Bibliographically approved

Open Access in DiVA

No full text

Other links

Publisher's full text

Search in DiVA

By author/editor
Tenhunen, Hannu
In the same journal
IET Circuits, Devices & Systems
Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

Altmetric score

Total: 25 hits
ReferencesLink to record
Permanent link

Direct link