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Exploring a Low-Cost and Power-Efficient Hybridization Technique for 3D NoC-Bus Hybrid Architecture Using LastZ-Based Routing Algorithms
University of Turku andTurku Centre for Computer Science (TUCS).
University of Turku.
University of Turku.
University of Turku.
2012 (English)In: Journal of Low Power Electronics, ISSN 1546-1998, Vol. 8, no 4, 403-414 p.Article in journal (Refereed) Published
Abstract [en]

Three-dimensional (3D) integration in which m ultiple active silicon layers are stacked above each other and vertically interconnected offers shorter interconnection wire for Networks-on-Chip (NoC). The simple 3D NoC architectures such as Symmetric 3D Mesh NoC could not exploit the beneficial feature of a negligible inter-layer dista nce in 3D chips. In order to exploit the intrinsic capability of reducing the wire length in 3D ICs, 3D NoC-Bus Hybrid architecture was proposed. This architecture suffers from naive and straightforward hybridization between NoC and bus media. In this paper, an efficient hybridization scheme is presented to enhance system performance, power consumption, and area of 3D NoC-Bus Hybrid architectures. The hybridization mechanism benefiting from a rule called LastZ enables low-cost inter-layer communication architecture. In the proposed architecture, instead of using the conventional 6×6 routers, 5×6 routers were utilized which offers many advantages. To estimate the efficiency of the proposed architecture, the system has been simulated using synthetic (uniform, hotspot 10%, and Negative Exponential Distribution) traffic patterns as well as real benchmarks, including the one with an integrated videoconference application. Compared to a conventional 3D NoC-Bus Hybrid Mesh architecture, our extensive simulations reveal significant area, power, and performance improvements for the proposed LastZ-based hybridization scheme.

Place, publisher, year, edition, pages
2012. Vol. 8, no 4, 403-414 p.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
URN: urn:nbn:se:kth:diva-111510DOI: 10.1166/jolpe.2012.1202ScopusID: 2-s2.0-84865169884OAI: diva2:586765

QC 20130115

Available from: 2013-01-12 Created: 2013-01-12 Last updated: 2015-07-29Bibliographically approved

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Tenhunen, Hannu
Electrical Engineering, Electronic Engineering, Information Engineering

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