Designing a High Performance and Reliable Networks-on-Chip Using Network Interface Assisted Routing Strategy
2012 (English)In: Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012, 2012, 34-41 p.Conference paper (Refereed)
Partial Virtual channel Sharing (PVS) architecture has been proposed to enhance the performance of Networks-on-Chip (NoC) based systems. In this paper, we present an efficient and reliable Network Interface (NI) assisted routing strategy for NoC using PVS architecture. For this purpose, NoC system is divided into clusters. Each cluster is a group of two nodes comprising Processing Elements (PE), switches, links, etc. Each PE in a cluster can inject data to the network through a router, which is closer to the destination. This helps to reduce the network load by reducing the average hop count of the network. The proposed architecture can recover the PE disconnected from the network due to network level faults by allowing the PE to transmit and receive the packets through the other router in the cluster. 5X6 crossbar is used for the proposed architecture which requires one more 5X1 multiplexer without increasing the critical path delay of the router as compared to the 5X5 crossbar. The proposed router has been simulated for uniform and negative exponential distribution (NED) traffic patterns. The simulation results show the significant reduction in average packet latency at the expense of negligible area overhead.
Place, publisher, year, edition, pages
2012. 34-41 p.
Network Interface (NI), Networks-on-Chip (NoC), Processing Element (PE) recovery, Virtual Channel (VC)
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-111504DOI: 10.1109/DSD.2012.43ScopusID: 2-s2.0-84872921989ISBN: 978-1-4673-2498-4OAI: oai:DiVA.org:kth-111504DiVA: diva2:586769
15th Euromicro Conference on Digital System Design (DSD), 2012
QC 201305232013-01-122013-01-122015-07-29Bibliographically approved