HLS-DoNoC: High-level simulator for dynamically organizational NoCs
2012 (English)In: Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2012 IEEE 15th International Symposium on, IEEE , 2012, 89-94 p.Conference paper (Refereed)
A high-level simulator is presented for the design and analysis of dynamically organizational Networks-on-Chip (DoNoCs). The DoNoC is able to organize statically or dynamically different network nodes for run-time coarse and fine grained reconfiguration, in particular power management. As an important step in the design flow, a simulator for early-stage design exploration is the focus of the paper. Built upon classic wormhole-based NoC architecture, the simulator is capable of experimenting diverse run-time monitoring and reconfiguration methods. In particular, dynamic clusterization can be performed with inter-cluster interfaces properly configured at the run-time. The simulator is flit-level accurate, trace-driven, and easy-to-reconfigure. It supports both synchronous and ratiochronous timing, and can provide the communication performance and power/energy consumption. The paper demonstrates the usage of the simulator in the design of various cluster-based power management schemes.
Place, publisher, year, edition, pages
IEEE , 2012. 89-94 p.
Cluster-based, Clusterization, Communication performance, Design and analysis, Design Exploration, Design flows, Fine grained, Network node, Networks on chips, NoC architectures, Power management scheme, Power managements, Runtime Monitoring, Runtimes
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-111491DOI: 10.1109/DDECS.2012.6219031ISI: 000312905700025ScopusID: 2-s2.0-84864364060ISBN: 978-146731185-4OAI: oai:DiVA.org:kth-111491DiVA: diva2:586780
2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012; Tallinn; 18 April 2012 through 20 April 2012
QC 201301302013-01-122013-01-122013-10-01Bibliographically approved