HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks
2012 (English)In: Proceedings of the 2012 6th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2012, 2012, 19-26 p.Conference paper (Refereed)
The occurrence of congestion in on-chip networks can severely degrade the performance due to increased message latency. In mesh topology, minimal methods can propagate messages over two directions at each switch. When shortest paths are congested, sending more messages through them can deteriorate the congestion condition considerably. In this paper, we present an adaptive routing algorithm for on-chip networks that provide a wide range of alternative paths between each pair of source and destination switches. Initially, the algorithm determines all permitted turns in the network including 180-degree turns on a single channel without creating cycles. The implementation of the algorithm provides the best usage of all allowable turns to route messages more adaptively in the network. On top of that, for selecting a less congested path, an optimized and scalable learning method is utilized. The learning method is based on local and global congestion information and can estimate the latency from each output channel to the destination region.
Place, publisher, year, edition, pages
2012. 19-26 p.
Adaptive Routing, Networks on chip, Non-Minimal Routing Algorithm, Q-Learning Methods
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-111485DOI: 10.1109/NOCS.2012.10ScopusID: 2-s2.0-84862726803OAI: oai:DiVA.org:kth-111485DiVA: diva2:586792
6th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2012; Copenhagen; Denmark
QC 201305232013-01-122013-01-122013-05-23Bibliographically approved