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Path-based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing
Turku Centre for Computer Science (TUCS).
Turku Centre for Computer Science (TUCS).
Turku Centre for Computer Science (TUCS).
Turku Centre for Computer Science (TUCS).
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2012 (English)In: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 99, 1-16 p.Article in journal (Refereed) Published
Abstract [en]

Combining the benefits of 3D ICs and Networks-on-Chip (NoCs) schemes provides a significant performance gain for 3D architectures. Since multicast communication is commonly used in cache coherence protocols for CMPs and in various parallel applications, the performance in these systems can be significantly improved if multicast operations are supported at hardware level. In this paper, we present several partitioning methods for the path-based multicast approach in 3D mesh-based NoCs, each with different levels of efficiency. In addition, we develop novel analytical models for unicast and multicast traffic to explore the efficiency of each approach. In order to distribute the unicast and multicast traffic more efficiently over the network, we propose Minimal Adaptive Routing (MAR) algorithm for the presented partitioning methods. The analytical and experimental results show that an advantageous method named Recursive Partitioning (RP) outperforms the other approaches. RP recursively partitions the network until all partitions contain a comparable number of switches and the multicast traffic is equally distributed among several subsets. The simulation results reveal that the RP method can achieve performance improvement across all workloads while the performance can be further improved by utilizing MAR, 19% average and 42% maximum latency reduction, on SPLASH-2 and PARSEC benchmarks.

Place, publisher, year, edition, pages
2012. Vol. 99, 1-16 p.
Keyword [en]
3D Networks-on-Chip, unicast and multicast communication, partitioning methods, analytical models, adaptive routing algorithm
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
URN: urn:nbn:se:kth:diva-111486DOI: 10.1109/TC.2012.255ISI: 000333471800016ScopusID: 2-s2.0-84897490992OAI: diva2:586793

QC 20130502

Available from: 2013-01-12 Created: 2013-01-12 Last updated: 2013-05-02Bibliographically approved

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Tenhunen, Hannu
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Electronic SystemsVinnExcellence Center for Intelligence in Paper and Packaging, iPACK
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Electrical Engineering, Electronic Engineering, Information Engineering

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