An integration approach for graphene double-gate transistors
2012 (English)In: Solid-State Device Research Conference (ESSDERC), 2012 Proceedings of the European, IEEE , 2012, 250-253 p.Conference paper (Refereed)
In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for microelectronics integration: bottom gates with ultra-thin (2nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing and other graphene-based devices.
Place, publisher, year, edition, pages
IEEE , 2012. 250-253 p.
, European Solid-State Device Research Conference, ISSN 1930-8876
Atomic layer deposited, Bottom gate, Double gate, Double-Gate transistor, High quality, Integration approach, Process flows, Process steps, Shallow trench isolation, Ultra-thin, Wafer-scale processing
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-111801DOI: 10.1109/ESSDERC.2012.6343380ScopusID: 2-s2.0-84870618571ISBN: 978-146731707-8OAI: oai:DiVA.org:kth-111801DiVA: diva2:587440
42nd European Solid-State Device Research Conference, ESSDERC 2012, 17 September 2012 through 21 September 2012, Bordeaux
QC 201301142013-01-142013-01-142013-09-03Bibliographically approved