Analytical approaches for performance evaluation of networks-on-chip
2012 (English)In: CASES'12 - Proceedings of the 2012 ACM International Conference on Compilers, Architectures and Synthesis for Embedded Systems, Co-located with ESWEEK, ACM , 2012, 211-212 p.Conference paper (Refereed)
This tutorial reviews four popular mathematical formalisms - dataflow analysis, schedulability analysis, network calculus, and queueing theory - and how they have been applied to the analysis of Network-on-Chip (NoC) performance. We review the basic concepts and results of each formalism and provide examples of how they have been used in on-chip communication performance analysis. The tutorial also discusses the respective strengths and weaknesses of each formalism, their suitability for a specific purpose, and the attempts that have been made to bridge these analytical approaches. Finally, we conclude the tutorial by discussing open research issues.
Place, publisher, year, edition, pages
ACM , 2012. 211-212 p.
Analytical modeling, Design methodology, Network-on-chip, Performance evaluation, System-on-chip
Engineering and Technology
IdentifiersURN: urn:nbn:se:kth:diva-114012DOI: 10.1145/2380403.2380442ISI: 000324163200028ScopusID: 2-s2.0-84869071319ISBN: 978-145031424-4OAI: oai:DiVA.org:kth-114012DiVA: diva2:588197
2012 ACM International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2012, Co-located with 8th Embedded Systems Week, ESWEEK 2012, 7 October 2012 through 12 October 2012, Tampere, Finland
QC 201301152013-01-152013-01-152013-12-06Bibliographically approved