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All Digital Polar Transmitter Design for Software Defined Radio: Architecture and Low Power Circuit Implementation
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. (iPack Wireless Link Project)
2012 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The evolving wireless communication technology is aiming highdata rate, high mobility, long distance and at the meantime, co-existwith various different standards. This developing trend requires ahighly linear transceiver system and it causes the problem of lowefficiency due to the large crest factor of signals. On the other hand,with process scaling, digital blocks are occupying more functions andchip area than before, to fully utilize the digital process low poweradvantage and save design cost, hardware reuse is preferable. Theconcept of Software Defined Radio (SDR) is raised to make thesystem more adaptable to multiple communication standards withminimal hardware resources.

In this doctoral dissertation work, the software defined radioarchitecture especially the all-digital polar transmitter architecture isexplored. System level comparison on different transmitter topologiesis carried out in the first place. Direct conversion, out-phasing andpolar transmitter topologies are compared. Based on the system levelevaluation, a Lowpass Sigma Delta Modulation (LPSDM) digitalpolar transmitter is designed under 90nm CMOS process andpackaged in QFN32. 19.3% peak efficiency and 11.4dBm outputpower is measured under single 1.0V supply. The constellationmeasurement achieved 5.08% for 3pi/8PSK modulation and 7.01%for QAM16 modulation output. The measurement on the packagedtransmitter AM/AM and AM/PM also demonstrated the linearity andpower efficiency performance under low voltage environment. This verified the possibility for a fully SDR solution in the future.

As a specific application and genuine creation, the UHF RFIDstandard is mapped into digital polar transmitter architecture. System level simulation is performed and transient signal parameters areextracted. To prove the SDR possibility, the system is fully designedby VHDL language and downloaded into FPGA hardware with highspeed serial port. The measured results confirm the possibility of thedigital polar transmitter architecture potential in SDR systemrealization.

Based on the design and verification of two different systems, themethodology for digital implementation of linear transmitter systemis developed and the skill to carry out optimization and measurementis also possessed. In conclusion, the academic publication andverification proved the feasibility of digital polar transmitterapplication in linear system and point out the direction for a fullySDR realization.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2012. , xviii, 96, 13, 17 p.
Series
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 12:10
Keyword [en]
Switching Power Amplifier, All Digital Polar Transmitter, Lowpass Sigma Delta Modulation, Software Defined Radio, RFID, H-Bridge Architecture, Resonating, Filter Matching Network.
National Category
Computer Systems
Research subject
SRA - ICT
Identifiers
URN: urn:nbn:se:kth:diva-116861ISBN: 978-91-7501-614-6 (print)OAI: oai:DiVA.org:kth-116861DiVA: diva2:601069
Public defence
2013-02-22, Forum Sal-D, Isafjordsgatan 39, Kista, 09:00 (English)
Opponent
Supervisors
Projects
iPack
Note

QC 20130129

Available from: 2013-01-29 Created: 2013-01-28 Last updated: 2013-01-29Bibliographically approved
List of papers
1. Systematic design of a flash ADC for UWB applications
Open this publication in new window or tab >>Systematic design of a flash ADC for UWB applications
2007 (English)In: 8th International Symposium on Quality Electronic Design, ISQED 2007: San Jose, CA; 26 March 2007 through 28 March 2007, 2007, 108-112 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents the systematic design of a 5-bit, 1.2 GSPS interpolative flash ADC for multiband OFDM UWB applications. The proposed ADC architecture employs the proven capacitive interpolation, which greatly reduce the power consumption, by eliminating the need of a power hungry resistive ladder The flash ADC has been implemented in a 0.18 um CMOS process. Circuit level simulations show that the proposed architecture can achieve an SNDR of 25.3 dB, and an SFDR of 29.3 dB, with an input signal frequency of 330 MHz, at a sampling rate of 1.2 GSPS. The ADC core dissipates 130 mW from a 1.8 V supply.

National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-14264 (URN)10.1109/ISQED.2007.155 (DOI)000246368000016 ()2-s2.0-34548138863 (Scopus ID)978-0-7695-2795-6 (ISBN)
Note
QC 20100729Available from: 2010-07-29 Created: 2010-07-29 Last updated: 2013-01-29Bibliographically approved
2. RF Transmitter Architecture Investigation for Power Efficient Mobile WiMAX Applications
Open this publication in new window or tab >>RF Transmitter Architecture Investigation for Power Efficient Mobile WiMAX Applications
Show others...
2008 (English)In: 2008 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS / [ed] Nurmi J, Takala J, Vainio O, NEW YORK: IEEE , 2008, 114-117 p.Conference paper, Published paper (Refereed)
Abstract [en]

Wireless broadband digital communication systems with high spectral efficiency suffer from severe power efficiency problem. Peak-to-Average Power Ratio is reported up to 12dB for WiMAX 802.16e systems implementing OFDM IFFT-1024 and 64-QAM modulation. In this work, outphasing (LILAC) and polar transmitter architectures are investigated and compared with direct conversion (DC) architecture. Complete system solution targeting 23dBm output power is evaluated. System level simulation result shows that, with linear power combiner, LILAC consumes more power than DC if non-clipping modulation scheme used. And polar system has stringent 3 degree phase matching and 0.5dB gain matching requirements to meet EVM and spectrum mask specifications.

Place, publisher, year, edition, pages
NEW YORK: IEEE, 2008
National Category
Electrical Engineering, Electronic Engineering, Information Engineering Computer and Information Science
Identifiers
urn:nbn:se:kth:diva-31542 (URN)10.1109/ISSOC.2008.4694883 (DOI)000262647700026 ()2-s2.0-67249124570 (Scopus ID)978-1-4244-2541-9 (ISBN)
Conference
10th Annual International Symposium on System-on-Chip Tampere, FINLAND, 2008
Note
QC 20110405Available from: 2011-04-05 Created: 2011-03-18 Last updated: 2013-01-29Bibliographically approved
3. A Switch Mode Resonating H-Bridge Polar Transmitter using RF Sigma Delta Modulation
Open this publication in new window or tab >>A Switch Mode Resonating H-Bridge Polar Transmitter using RF Sigma Delta Modulation
2010 (English)In: IEEE INT SYMP CIRC SYST PROC, 2010, 1911-1914 p.Conference paper, Published paper (Refereed)
Abstract [en]

Using saturated power amplifier (PA) as the last stage, polar transmitter has the potential to be the most power efficient architecture to transmit large Peak-to-Average Ratio (PAR) signals. In this work, a polar transmitter using H-Bridge configured Class-D amplifiers is proposed. To fully exploit low voltage resource, maintain linearity and meet the spectrum mask requirements, RF Sigma-Delta Modulation (SDM) is used. An on-chip transformer based filter network is designed to filter out SDM noise and provide load matching. The system verification is carried out by using Matlab passband simulation on a 13dB PAR mobile WiMAX signal. Evaluation of noise shaping and spectral regrowth shows the proposed architecture can achieve -45dBc/10kHz ACPR in a 140MHz bandwidth range. This provides a solid ground for the circuit design work.

Series
IEEE International Symposium on Circuits and Systems, ISSN 0271-4302
Keyword
Polar Architecture, Sigma-Delta Modulation, Class-D Power Amplifier
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-32139 (URN)10.1109/ISCAS.2010.5537969 (DOI)000287216002034 ()2-s2.0-77955995322 (Scopus ID)978-1-4244-5309-2 (ISBN)
Conference
International Symposium on Circuits and Systems Nano-Bio Circuit Fabrics and Systems (ISCAS 2010)
Note

QC 20110407

Available from: 2011-04-07 Created: 2011-04-07 Last updated: 2013-01-29Bibliographically approved
4. A polar transmitter architecture with digital switching amplifier for UHF RFID applications
Open this publication in new window or tab >>A polar transmitter architecture with digital switching amplifier for UHF RFID applications
2011 (English)In: 5th Annual IEEE International Conference on RFID, IEEE , 2011, 1-6 p.Conference paper, Published paper (Refereed)
Abstract [en]

With amplitude shift keying (ASK) modulation and signal envelope rising falling edge slope requirements, the efficiency of UHF RFID system can be improved by using polar transmitter architecture than using linear power amplifiers. In this work, to ensure maximum integration and meet EPC Class-1 Generation-2 specification, an all digital polar transmitter is proposed and verified by transient signal analysis and random pattern simulation. The timing and signal quality constraints of the digital polar transmitter circuits are extracted. Due to the use of RF frequency low pass sigma delta modulation, the system can be designed in pure digital process without on-chip inductive components. Compared to the 31% theoretical efficiency by using class-A linear power amplifier, a minimum 77% theoretical efficiency can be achieved in this proposed digital RFID system.

Place, publisher, year, edition, pages
IEEE, 2011
Keyword
UHF RFID, RF sigma delta modulation, all digital polar transmitter, inductance less all digital process
National Category
Telecommunications
Identifiers
urn:nbn:se:kth:diva-49130 (URN)10.1109/RFID.2011.5764612 (DOI)2-s2.0-79957437655 (Scopus ID)978-1-4244-9607-5 (ISBN)
Conference
2011 IEEE International Conference on RFID (RFID)
Note
QC 20120109Available from: 2012-01-09 Created: 2011-11-25 Last updated: 2013-01-29Bibliographically approved
5. All-digital transmitter based on ADPLL and phase synchronized delta sigma modulator
Open this publication in new window or tab >>All-digital transmitter based on ADPLL and phase synchronized delta sigma modulator
2011 (English)In: Radio Frequency Integrated Circuits Symposium (RFIC), 2011 IEEE, IEEE , 2011, 1-4 p.Conference paper, Published paper (Refereed)
Abstract [en]

A novel architecture of all-digital polar transmitters is proposed, mainly composed of an all digital PLL (ADPLL) for phase modulation, a 1-bit low-pass delta sigma (ΔΣ) modulator for envelop modulation and a high efficiency class-D PA. The low noise ADPLL and high oversample ΔΣ modulator relax filter design, enabling the use of a on-chip filter. The differential signaling scheme enhances the power of the fundamental tone and suppresses DC and high harmonics. The transmitter was fabricated in a 90nm digital CMOS process, occupying 1.4 mm2. The measurement results demonstrate effectiveness of the architecture. The digital transmitter consumes 58 mW power from a 1 V supply, delivering a 6.81-dBm output.

Place, publisher, year, edition, pages
IEEE, 2011
Series
IEEE, ISSN 1529-2517
Keyword
ADPLL, All digital, Delta Sigma, polar transmitter, transmitter
National Category
Telecommunications
Identifiers
urn:nbn:se:kth:diva-62144 (URN)10.1109/RFIC.2011.5940595 (DOI)2-s2.0-79960766547 (Scopus ID)978-1-4244-8293-1 (ISBN)
Conference
Radio Frequency Integrated Circuits Symposium (RFIC), 2011 IEEE
Projects
iPack Vinn Excellence Center
Note
QC 20120201Available from: 2012-02-15 Created: 2012-01-18 Last updated: 2013-02-28Bibliographically approved
6. A 11.4dBm 90nm CMOS H-Bridge Resonating Polar Amplifier using RF Sigma Delta Modulation
Open this publication in new window or tab >>A 11.4dBm 90nm CMOS H-Bridge Resonating Polar Amplifier using RF Sigma Delta Modulation
2011 (English)In: Proceedings of the ESSCIRC (ESSCIRC), 2011, IEEE , 2011, 307-310 p.Conference paper, Published paper (Refereed)
Abstract [en]

Using RF Sigma Delta Modulation (RFSDM), aclass-D polar amplifier in H-Bridge configuration can work in resonatingmode and minimize the switching loss for high efficiencypolar transmitters. The high oversampling ratio envelop bitstream created by the low pass RFSDM is phase modulated anddigitally mixed with quantized RF carrier to give a modulatedRF digital signal. By taking the advantage of high speed andaccurate digital CMOS process, this ’information combination’architecture can achieve high efficiency and reduce the need forexternal filter components. A polar power amplifier based on thisconcept is implemented in 90nm CMOS process and achieved apeak output power of 11.4dBm with 19.3% efficiency at 1.0Vpower supply. The total area is 0.72mm2 including an on-chipfilter matching network designed for 2.4GHz to 2.7GHz band.

Place, publisher, year, edition, pages
IEEE, 2011
Keyword
Low Pass RF Sigma Delta Modulation, H-Bridge Digital Polar Amplifier, on-Chip Filter Matching Network, Digital Delay Trimming
National Category
Communication Systems
Identifiers
urn:nbn:se:kth:diva-72181 (URN)10.1109/ESSCIRC.2011.6044968 (DOI)2-s2.0-82955241335 (Scopus ID)978-1-4577-0703-2 (ISBN)
Conference
ESSCIRC 2011
Note
Qc 20120203Available from: 2012-02-03 Created: 2012-01-31 Last updated: 2013-01-29Bibliographically approved
7. The Design of All-Digital Polar Transmitter based on ADPLL and Phase Synchronized Delta Sigma Modulator
Open this publication in new window or tab >>The Design of All-Digital Polar Transmitter based on ADPLL and Phase Synchronized Delta Sigma Modulator
Show others...
2012 (English)In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 47, no 5, 1154-1164 p.Article in journal (Refereed) Published
Abstract [en]

An improved architecture of polar transmitter (TX) is presented. The proposed architectureis digitally-intensive and mainly composed of an all-digital PLL (ADPLL) for phasemodulation, a 1-bit low-pass delta sigma (Delta Sigma) modulator for envelop modulation, and aH-bridge class-D power amplifier (PA) for differential signaling. The (Delta Sigma) modulator isclocked using the phase modulated RF carrier to ensure phase synchronization between theamplitude and phase path, and to guarantee the PA is switching at zero crossings of theoutput current.An on chip pre-filter is used to reduce the parasitic capacitance from packages at theswitch stage output. The high over sampling ratio of the (Delta Sigma) modulator move quantizationnoise far away from the carrier frequency, ensuring good in-band performance and relax filterrequirements. The on-chip filter also acts as impedance matching and differential to singleended conversion. The measured digital transmitter consumes 58 mW from a 1 V at 6.8 dBm output power.

Place, publisher, year, edition, pages
IEEE Solid-State Circuits Society, 2012
Keyword
All digital, polar transmitter, transmitter, ADPLL, Delta Sigma
National Category
Telecommunications
Identifiers
urn:nbn:se:kth:diva-72240 (URN)10.1109/JSSC.2012.2186720 (DOI)000303329600010 ()2-s2.0-84860475717 (Scopus ID)
Projects
iPack
Funder
ICT - The Next Generation
Note

© 2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

QC 20120503

Available from: 2012-05-03 Created: 2012-01-31 Last updated: 2017-12-08Bibliographically approved

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