Segmented bus based path setup scheme for a distributed memory architecture
2012 (English)In: Proceedings - IEEE 6th International Symposium on Embedded Multicore SoCs, MCSoC 2012, IEEE , 2012, 67-74 p.Conference paper (Refereed)
This paper proposes a composite instruction for path setup and partitioning of a network on chip using segmented buses. The network connects a distributed memory to a coarse grained reconfigurable architecture. The scheme decreases the partitioning and routing instruction in sequencers (S) for the nodes (N) from Nx3 to a single instruction. This reduction in instruction also bear a small performance benefit as less instructions are scheduled onto the network. Furthermore, it is possible to optimizing the system under application specificconstraints. A simple use-case with experiments is defined to show for design trade-offs for these optimization decisions.
Place, publisher, year, edition, pages
IEEE , 2012. 67-74 p.
CGRA, Coarse grained reconfigurable architecture, DiMArch, Distributed memory system, DRRA, Memory Systems, Network on Chip, NOC, Path Setup, Segmented Buses, SYLVA, VESYLA
Engineering and Technology
IdentifiersURN: urn:nbn:se:kth:diva-116812DOI: 10.1109/MCSoC.2012.34ScopusID: 2-s2.0-84872573163OAI: oai:DiVA.org:kth-116812DiVA: diva2:601425
2012 IEEE 6th International Symposium on Embedded Multi-Core Systems on Chips, MCSoC 2012, 20 September 2012 through 22 September 2012, Aizu-Wakamatsu, Fukushima
QC 201301292013-01-292013-01-282013-01-29Bibliographically approved