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A survey of FPGA dynamic reconfiguration design methodology and applications
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0061-3475
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
2012 (English)In: International Journal of Embedded and Real-Time Communication Systems, ISSN 1947-3176, Vol. 3, no 2, 23-39 p.Article, review/survey (Refereed) Published
Abstract [en]

FPGA Dynamic Partial Reconfiguration (DPR or PR) technology has emerged and become gradually mature in the recent years. It provides the Time-Division Multiplexing (TDM) capability in utilizing on-chip resources and leads to significant benefits in comparison with conventional static designs. However, the partially reconfigurable design process features additional complexity and technical requirements to the FPGA developers. Hence, PR design approaches are being widely explored and investigated to systematize the development methodology and ease the designers. In this paper, the authors collect several research and engineering projects in this area and present a survey of the design methodology and applications of PR. Research aspects are discussed in various hardware/software layers.

Place, publisher, year, edition, pages
2012. Vol. 3, no 2, 23-39 p.
Keyword [en]
Adaptive computing, FPGA partialre configuration, Reconfigurable computing, Time division multiplexing
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-118364DOI: 10.4018/jertcs.2012040102Scopus ID: 2-s2.0-84872918817OAI: oai:DiVA.org:kth-118364DiVA: diva2:606022
Note

QC 20130218

Available from: 2013-02-18 Created: 2013-02-15 Last updated: 2013-02-18Bibliographically approved

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Lu, Zhonghai

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