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Artificial neural network emulation on NOC based multi-core FPGA platform
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0002-8072-1742
2012 (English)In: NORCHIP, 2012, IEEE , 2012, 6403122- p.Conference paper, Published paper (Refereed)
Abstract [en]

With the emergence of Multi-Core platforms, brain emulation in the form of Artificial Neural Nets has been announced as one of the important key research area. However, due to large non-linear growth of inter-neuron connectivity, direct mapping of ANNs to silicon structures is very difficult due to communication bottleneck.

Place, publisher, year, edition, pages
IEEE , 2012. 6403122- p.
Keyword [en]
ANN, Fast-prototyping, FPGA, NOC, SW/HW
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-118514DOI: 10.1109/NORCHP.2012.6403122ISI: 000332453500027Scopus ID: 2-s2.0-84873561138ISBN: 978-146732221-8 (print)OAI: oai:DiVA.org:kth-118514DiVA: diva2:606633
Conference
NORCHIP 2012 Conference, 12 November 2012 through 13 November 2012, Copenhagen
Note

QC 20130220

Available from: 2013-02-20 Created: 2013-02-20 Last updated: 2014-10-14Bibliographically approved
In thesis
1. A model-based design approach for heterogeneous NoC-based MPSoCs on FPGA
Open this publication in new window or tab >>A model-based design approach for heterogeneous NoC-based MPSoCs on FPGA
2014 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

Network-on-chip (NoC) based multi-processor systems-on-chip (MPSoCs) are promising candidates for future multi-processor embedded platforms, which are expected to be composed of hundreds of heterogeneous processing elements (PEs) to potentially provide high performances. However, together with the performances, the systems complexity will increase, and new high level design techniques will be needed to efficiently model, simulate, debug and synthesize them. System-level design (SLD) is considered to be the next frontier in electronic design automation (EDA). It enables the description of embedded systems in terms of abstract functions and interconnected blocks. A promising complementary approach to SLD is the use of models of computation (MoCs) to formally describe the execution semantics of functions and blocks through a set of rules. However, also when this formalization is used, there is no clear way to synthesize system-level models into software (SW) and hardware (HW) towards a NoC-based MPSoC implementation, i.e., there is a lack of system design automation (SDA) techniques to rapidly synthesize and prototype system-level models onto heterogeneous NoC-based MPSoCs. In addition, many of the proposed solutions require large overhead in terms of SW components and memory requirements, resulting in complex and customized multi-processor platforms. In order to tackle the problem, a novel model-based SDA flow has been developed as part of the thesis. It starts from a system-level specification, where functions execute according to the synchronous MoC, and then it can rapidly prototype the system onto an FPGA configured as an heterogeneous NoC-based MPSoC. In the first part of the thesis the HeartBeat model is proposed as a model-based technique which fills the abstraction gap between the abstract system-level representation and its implementation on the multiprocessor prototype. Then details are provided to describe how this technique is automated to rapidly prototype the modeled system on a flexible platform, permitting to adjust the system specification until the designer is satisfied with the results. Finally, the proposed SDA technique is improved defining a methodology to automatically explore possible design alternatives for the modeled system to be implemented on a heterogeneous NoC-based MPSoC. The goal of the exploration is to find an implementation satisfying the designer's requirements, which can be integrated in the proposed SDA flow. Through the proposed SDA flow, the designer is relieved from implementation details and the design time of systems targeting heterogeneous NoC-based MPSoCs on FPGA is significantly reduced. In addition, it reduces possible design errors proposing a completely automated technique for fast prototyping. Compared to other SDA flows, the proposed technique targets a bare-metal solution, avoiding the use of an operating system (OS). This reduces the memory requirements on the FPGA platform comparing to related work targeting MPSoC on FPGA. At the same time, the performance (throughput) of the modeled applications can be increased when the number of processors of the target platform is increased. This is shown through a wide set of case studies implemented on FPGA.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2014. 88 p.
Series
TRITA-ICT-ECS AVH, ISSN 1653-6363 ; 14:10
Keyword
System-level design;platform-based designembedded systems;field programmable gate arrays;integrated circuit design;integrated circuit modelling;network-on-chip;FPGA;NoC-based MPSoC;Simulink;common semantics domain;dataflow applications;design flow;embedded system;multiprocessor systems;network-on-chip;Computational modeling;Field programmable gate arrays;Mathematical model;Program processors;Prototypes;Semantics;
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-145521 (URN)978-91-7595-150-8 (ISBN)
Presentation
2014-06-13, Sal/Hall E, KTH - ICT, Isafjordsgatan 39, Kista, 10:00 (English)
Opponent
Supervisors
Note

QC 20140609

Available from: 2014-06-09 Created: 2014-05-21 Last updated: 2014-06-09Bibliographically approved

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