Testing of an off-chip NoC protocol using a BIST/Synthesizable Testbench approach
2012 (English)In: NORCHIP, 2012, IEEE , 2012, 6403128- p.Conference paper (Refereed)
To make systems infinitely scalable is the holy grail of chip design and crux that needs to be solved in order to invent a sustainable design methodology. Network-on-Chip (NoC) has been suggested as this solution as it replaces the traditional buses for on-chip interconnection purposes. However, to reach infinite scalability, off-chip extensions to the NoC protocols are needed in order to maintain scalability at an affordable cost of manufacturability. Going off-chip introduces more levels of complexity when it comes to testing, not only should the chip testing be speedy, the off-chip connections must also be testable in a fast manner, the fastest way being a set of BISTs testing the whole structure in parallel. In this paper, we present a BIST approach for testing an off-chip NoC protocol used in a 4x4 Network-on-Chip configuration. It has 16 processor-nodes implemented on four interconnected plesiochronous Altera Stratix-II FPGA boards, each board hosting a Quad-core NoC.
Place, publisher, year, edition, pages
IEEE , 2012. 6403128- p.
Built-in Self Test, interconnect, multi-core, Network-on-Chip, off-chip/inter-board NoC protocol, on-chip NoC protocol, plesiochronous clocking
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-118503DOI: 10.1109/NORCHP.2012.6403128ISI: 000332453500033ScopusID: 2-s2.0-84873563702ISBN: 978-146732221-8OAI: oai:DiVA.org:kth-118503DiVA: diva2:606653
NORCHIP 2012 Conference, 12 November 2012 through 13 November 2012, Copenhagen
QC 201302202013-02-202013-02-202014-10-14Bibliographically approved