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Experimental Validation of Device Sizing on CMOS LC-VCO Phase Noise
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
(iPack, KTH-ICT)
(Catena Wireless Electronics AB)
(Catena Wireless Electronics AB)
Show others and affiliations
(English)Manuscript (preprint) (Other academic)
Abstract [en]

This work investigates the impact of device sizingon phase noise in CMOS LC-tank oscillators, based on specificdesigns and careful measurements. It experimentally verified thepreviously published equations and clarified some conflictingdesign guidelines. The conclusions are grounded on the faircomparison of seven VCOs with the core device width varyingfrom 40 um to 280 um. These VCOs are originated from the samedie by using Focused Ion Beam (FIB), guaranteeing the sameorder of process variation. With the aid of a switched capacitorbank, they are able to operate at practically same oscillationfrequency under the same bias. These conditions assure the faircomparison. It validated that phase noise from tail devices isstrongly dependent to core device size (14 dB from measurements)while phase noise from core devices themselves shows smallerdependence (4 dB). Design guidelines, applying to different tailnoise cases, are concluded and generally advise the minimumcore device width especially when tail noise is dominant.

Keyword [en]
Oscillators, sizing, phase noise, LC-tank, CMOS
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-118817OAI: oai:DiVA.org:kth-118817DiVA: diva2:608566
Note

QS 2013

Available from: 2013-02-28 Created: 2013-02-28 Last updated: 2013-02-28Bibliographically approved
In thesis
1. Low Noise Oscillator in ADPLL toward Direct-to-RF All-digital Polar Transmitter
Open this publication in new window or tab >>Low Noise Oscillator in ADPLL toward Direct-to-RF All-digital Polar Transmitter
2012 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

In recent years all-digital or digitally-intensive RF transmitters (TX) have attracted great attention in both literature and industry. The motivation is to implement RF circuits in a manner suiting advanced nanometer CMOS processes. To achieve that, information is encoded in the time-domain rather than voltage amplitude. This enables RF design to also benefit from CMOS process scaling. In this thesis an improved architecture of a digitally-intensive transmitter is proposed and validated experimentally. The techniques to lower oscillator phase noise and all-digital phase-locked loop (ADPLL) quantization noise are discussed and proved by both simulation and measurements.

The impact of device sizing on 1/f^2 phase noise is analyzed and validated by measurements. Seven oscillators in 180-nm CMOS with the same LC-tank, operation frequency and power consumption but different core device width are compared. The conclusion clarify the different suggestions on device sizing in the literature. It is illustrated that tail noise contribution is strongly positive dependent to core device sizing, while the contribution of core devices themselves is weakly dependent. Measurements demonstrate that there is a 14-dB phase noise increase when sizing core devices from 40 um to 280 um in the case of noisy tail current. If tail current is clean, the increase is only 4 dB.  For 1/f^3 phase noise, the investigation reveals that the capacitance modulation is the dominant factor accounting for the 1/f or flick noise up-conversion, which is proved by measurements of 180-nm CMOS designs.   A class-C oscillator with ensured start-up and constant amplitude is presented. It achieves a 3.9-dB phase noise reduction in theory and 5-dB reduction in measurements, compared to a conventional LC-tank oscillator operating at the same frequency and power. With the help of a digital bias voltage and bias current control loop, a 191 Figure-of-Merit (FoM) is achieved, showing the ability for low power and noise application.   The previous oscillator optimization techniques have been applied in designing a digital controlled oscillator (DCO) for an ADPLL. A fine tuning varactor is proposed to reduce quantization noise, achieving a frequency step of only several hundreds Hz. In order to measure this small frequency step when the DCO is free-running, a method based on the narrow-band frequency modulation (FM) theory is proposed. The ADPLL wide-band FM is fulfilled by using a digital two-point modulation so that the modulation bandwidth is not limited by the ADPLL loop dynamic.

Finally an all-digital polar TX is proposed based on an improved architecture. The ADPLL is used for FM while a one-bit low-pass Sigma Delta modulator using the phase modulated ADPLL output as the clock accomplishes amplitude modulation. A simple AND gate is adopted to increase the fundamental power as mixers. A class-D power amplifier stages diliver 6.8-dBm power to antenna through a on-chip band-pass pre-filter. The filter also acts as single-ended to differential-end conversion and matching network.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2012. xi, 97 p.
Series
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 13:03
Keyword
all-digital, digitally-intensive, frequency modualtion, phase modulation, amplitude modulation, polar, transmitter, oscillator, digital controled oscillator, DCO, VCO, voltage controled oscillator, class-C oscillator, class-D PA, ADPLL, phase noise, RF, CMOS.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-118818 (URN)978-91-7501-643-6 (ISBN)
Public defence
2013-03-13, Sal D, KTH-Forum, Isafjordsgatan 39, Kista, 09:00 (English)
Opponent
Supervisors
Available from: 2013-02-28 Created: 2013-02-28 Last updated: 2013-02-28Bibliographically approved

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