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Low Noise Oscillator in ADPLL toward Direct-to-RF All-digital Polar Transmitter
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
2012 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

In recent years all-digital or digitally-intensive RF transmitters (TX) have attracted great attention in both literature and industry. The motivation is to implement RF circuits in a manner suiting advanced nanometer CMOS processes. To achieve that, information is encoded in the time-domain rather than voltage amplitude. This enables RF design to also benefit from CMOS process scaling. In this thesis an improved architecture of a digitally-intensive transmitter is proposed and validated experimentally. The techniques to lower oscillator phase noise and all-digital phase-locked loop (ADPLL) quantization noise are discussed and proved by both simulation and measurements.

The impact of device sizing on 1/f^2 phase noise is analyzed and validated by measurements. Seven oscillators in 180-nm CMOS with the same LC-tank, operation frequency and power consumption but different core device width are compared. The conclusion clarify the different suggestions on device sizing in the literature. It is illustrated that tail noise contribution is strongly positive dependent to core device sizing, while the contribution of core devices themselves is weakly dependent. Measurements demonstrate that there is a 14-dB phase noise increase when sizing core devices from 40 um to 280 um in the case of noisy tail current. If tail current is clean, the increase is only 4 dB.  For 1/f^3 phase noise, the investigation reveals that the capacitance modulation is the dominant factor accounting for the 1/f or flick noise up-conversion, which is proved by measurements of 180-nm CMOS designs.   A class-C oscillator with ensured start-up and constant amplitude is presented. It achieves a 3.9-dB phase noise reduction in theory and 5-dB reduction in measurements, compared to a conventional LC-tank oscillator operating at the same frequency and power. With the help of a digital bias voltage and bias current control loop, a 191 Figure-of-Merit (FoM) is achieved, showing the ability for low power and noise application.   The previous oscillator optimization techniques have been applied in designing a digital controlled oscillator (DCO) for an ADPLL. A fine tuning varactor is proposed to reduce quantization noise, achieving a frequency step of only several hundreds Hz. In order to measure this small frequency step when the DCO is free-running, a method based on the narrow-band frequency modulation (FM) theory is proposed. The ADPLL wide-band FM is fulfilled by using a digital two-point modulation so that the modulation bandwidth is not limited by the ADPLL loop dynamic.

Finally an all-digital polar TX is proposed based on an improved architecture. The ADPLL is used for FM while a one-bit low-pass Sigma Delta modulator using the phase modulated ADPLL output as the clock accomplishes amplitude modulation. A simple AND gate is adopted to increase the fundamental power as mixers. A class-D power amplifier stages diliver 6.8-dBm power to antenna through a on-chip band-pass pre-filter. The filter also acts as single-ended to differential-end conversion and matching network.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2012. , xi, 97 p.
Series
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 13:03
Keyword [en]
all-digital, digitally-intensive, frequency modualtion, phase modulation, amplitude modulation, polar, transmitter, oscillator, digital controled oscillator, DCO, VCO, voltage controled oscillator, class-C oscillator, class-D PA, ADPLL, phase noise, RF, CMOS.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-118818ISBN: 978-91-7501-643-6 (print)OAI: oai:DiVA.org:kth-118818DiVA: diva2:608575
Public defence
2013-03-13, Sal D, KTH-Forum, Isafjordsgatan 39, Kista, 09:00 (English)
Opponent
Supervisors
Available from: 2013-02-28 Created: 2013-02-28 Last updated: 2013-02-28Bibliographically approved
List of papers
1. Sizing of MOS device in LC-tank oscillators
Open this publication in new window or tab >>Sizing of MOS device in LC-tank oscillators
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2007 (English)In: 2007 Norchip, 2007, 90-95 p.Conference paper, Published paper (Refereed)
Abstract [en]

Since previous publications show conflicting results about sizing device, relationship between device size and 1/f(2) phase noise is studied and closed-form equations are derived in order to help designers to size devices in LC-tank oscillators for good phase noise performance. The analysis is divided into two steps. Firstly, periodic noise transfer functions of each VCO noise source to the output of switch FETs are derived, and the impact of sizing on these functions is discussed. Secondly, phase noise equations are derived with these functions. Experiments show that phase noise predicted by the equations agrees with that from simulations.

National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-40719 (URN)10.1109/NORCHP.2007.4481046 (DOI)000257311000021 ()2-s2.0-50249095023 (Scopus ID)978-1-4244-1516-8 (ISBN)
Conference
25th Norchip Conference Location: Aalborg, Denmark, Date: NOV 19-20, 2007
Note

QC 20160427

Available from: 2011-09-23 Created: 2011-09-20 Last updated: 2016-04-27Bibliographically approved
2. Experimental Validation of Device Sizing on CMOS LC-VCO Phase Noise
Open this publication in new window or tab >>Experimental Validation of Device Sizing on CMOS LC-VCO Phase Noise
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(English)Manuscript (preprint) (Other academic)
Abstract [en]

This work investigates the impact of device sizingon phase noise in CMOS LC-tank oscillators, based on specificdesigns and careful measurements. It experimentally verified thepreviously published equations and clarified some conflictingdesign guidelines. The conclusions are grounded on the faircomparison of seven VCOs with the core device width varyingfrom 40 um to 280 um. These VCOs are originated from the samedie by using Focused Ion Beam (FIB), guaranteeing the sameorder of process variation. With the aid of a switched capacitorbank, they are able to operate at practically same oscillationfrequency under the same bias. These conditions assure the faircomparison. It validated that phase noise from tail devices isstrongly dependent to core device size (14 dB from measurements)while phase noise from core devices themselves shows smallerdependence (4 dB). Design guidelines, applying to different tailnoise cases, are concluded and generally advise the minimumcore device width especially when tail noise is dominant.

Keyword
Oscillators, sizing, phase noise, LC-tank, CMOS
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-118817 (URN)
Note

QS 2013

Available from: 2013-02-28 Created: 2013-02-28 Last updated: 2013-02-28Bibliographically approved
3. Flicker noise conversion in CMOS LC oscillators: capacitance modulation dominance and core device sizing
Open this publication in new window or tab >>Flicker noise conversion in CMOS LC oscillators: capacitance modulation dominance and core device sizing
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2011 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 68, no 2, 145-154 p.Article in journal (Refereed) Published
Abstract [en]

Flicker noise upconversion mechanisms in oscillators have been acquired in the literature, however their relative weights are still under investigation. It is desirable to find the dominant one, since a certain noise suppression method reduces one mechanism but may increase another. In this work, we propose a systematic simulation method to distinguish their relative impacts. The outcome indicates parasitic capacitance is the dominant factor for both tail 1/f noise and switch pair 1/f noise upconversions, implying to use small dimension core devices. Design guidelines on sizing devices are presented and two suppression techniques are compared. Two voltage-controlled oscillators (VCOs) with these suppression techniques are fabricated in a 0.18 mu m CMOS process, allowing us to compare their performance. The two VCOs can be Focused-Ion-Beam (FIB) trimmed to change the width of switch pair FETs. The fair comparison of measurement results among them verify the dominant role of parasitic capacitance in 1/f noise upconversion. The measurement results also confirm the design guidelines and demonstrate the difference of two suppression methods.

Keyword
Oscillator, VCO, Device sizing, Flicker noise, 1/f noise, Phase noise
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-37144 (URN)10.1007/s10470-011-9650-5 (DOI)000292649900002 ()2-s2.0-80052441633 (Scopus ID)
Funder
ICT - The Next Generation
Available from: 2011-08-03 Created: 2011-08-02 Last updated: 2017-12-08Bibliographically approved
4. A Current Shaping Technique to Lower Phase Noise in LC Oscillators
Open this publication in new window or tab >>A Current Shaping Technique to Lower Phase Noise in LC Oscillators
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2008 (English)In: 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008: St. Julian's; 31 August 2008 through 3 September 2008, 2008, 392-395 p.Conference paper, Published paper (Refereed)
Keyword
Oscillators (electronic); Phase noise; Tanks (containers); Active devices; Bias noises; Closed forms; LC oscillators; Lc tanks; Noise equations; Phase noise performances; Shaping techniques
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-8289 (URN)10.1109/ICECS.2008.4674873 (DOI)2-s2.0-57849164229 (Scopus ID)
Conference
IEEE ICECS 2008
Note

QC 20100817

Available from: 2008-04-25 Created: 2008-04-25 Last updated: 2016-04-27Bibliographically approved
5. A Low Power, Startup Ensured and Constant Amplitude Class-C VCO in 0.18 mu m CMOS
Open this publication in new window or tab >>A Low Power, Startup Ensured and Constant Amplitude Class-C VCO in 0.18 mu m CMOS
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2011 (English)In: IEEE Microwave and Wireless Components Letters, ISSN 1531-1309, E-ISSN 1558-1764, Vol. 21, no 8, 427-429 p.Article in journal (Refereed) Published
Abstract [en]

A low power and robust class-C voltage-controlled oscillator (VCO) is presented in this letter. It features 1) an automatic startup loop to achieve the optimal point and address the inherent risk of startup failure and 2) a digital amplitude control loop to stabilize amplitude and enhance the PVT ( process, voltage and temperature) tolerance. The design is implemented in a 0.18 mu m CMOS process. Measurement demonstrates the VCO has a 20% tuning range and phase noise of -123.0 dBc/Hz at 1 MHz offset from a 3.1 GHz carrier while consuming 1.57-mW power from a 1 V supply, yielding a Figure-of-Merit (FoM) of 191.1. While operating under the minimum power of 560 mu W, it produces -111.3 dBc/Hz phase noise at 1 MHz offset from a 3.1 GHz carrier showing a 183.8 FoM.

Keyword
Class-C, current shaping, phase noise, pulse wave, startup, voltage controlled oscillator (VCO)
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-38979 (URN)10.1109/LMWC.2011.2160620 (DOI)000293754300011 ()2-s2.0-80051788038 (Scopus ID)
Funder
ICT - The Next Generation
Available from: 2011-09-05 Created: 2011-09-05 Last updated: 2017-12-08Bibliographically approved
6. All-digital transmitter based on ADPLL and phase synchronized delta sigma modulator
Open this publication in new window or tab >>All-digital transmitter based on ADPLL and phase synchronized delta sigma modulator
2011 (English)In: Radio Frequency Integrated Circuits Symposium (RFIC), 2011 IEEE, IEEE , 2011, 1-4 p.Conference paper, Published paper (Refereed)
Abstract [en]

A novel architecture of all-digital polar transmitters is proposed, mainly composed of an all digital PLL (ADPLL) for phase modulation, a 1-bit low-pass delta sigma (ΔΣ) modulator for envelop modulation and a high efficiency class-D PA. The low noise ADPLL and high oversample ΔΣ modulator relax filter design, enabling the use of a on-chip filter. The differential signaling scheme enhances the power of the fundamental tone and suppresses DC and high harmonics. The transmitter was fabricated in a 90nm digital CMOS process, occupying 1.4 mm2. The measurement results demonstrate effectiveness of the architecture. The digital transmitter consumes 58 mW power from a 1 V supply, delivering a 6.81-dBm output.

Place, publisher, year, edition, pages
IEEE, 2011
Series
IEEE, ISSN 1529-2517
Keyword
ADPLL, All digital, Delta Sigma, polar transmitter, transmitter
National Category
Telecommunications
Identifiers
urn:nbn:se:kth:diva-62144 (URN)10.1109/RFIC.2011.5940595 (DOI)2-s2.0-79960766547 (Scopus ID)978-1-4244-8293-1 (ISBN)
Conference
Radio Frequency Integrated Circuits Symposium (RFIC), 2011 IEEE
Projects
iPack Vinn Excellence Center
Note
QC 20120201Available from: 2012-02-15 Created: 2012-01-18 Last updated: 2013-02-28Bibliographically approved
7. The Design of All-Digital Polar Transmitter based on ADPLL and Phase Synchronized Delta Sigma Modulator
Open this publication in new window or tab >>The Design of All-Digital Polar Transmitter based on ADPLL and Phase Synchronized Delta Sigma Modulator
Show others...
2012 (English)In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 47, no 5, 1154-1164 p.Article in journal (Refereed) Published
Abstract [en]

An improved architecture of polar transmitter (TX) is presented. The proposed architectureis digitally-intensive and mainly composed of an all-digital PLL (ADPLL) for phasemodulation, a 1-bit low-pass delta sigma (Delta Sigma) modulator for envelop modulation, and aH-bridge class-D power amplifier (PA) for differential signaling. The (Delta Sigma) modulator isclocked using the phase modulated RF carrier to ensure phase synchronization between theamplitude and phase path, and to guarantee the PA is switching at zero crossings of theoutput current.An on chip pre-filter is used to reduce the parasitic capacitance from packages at theswitch stage output. The high over sampling ratio of the (Delta Sigma) modulator move quantizationnoise far away from the carrier frequency, ensuring good in-band performance and relax filterrequirements. The on-chip filter also acts as impedance matching and differential to singleended conversion. The measured digital transmitter consumes 58 mW from a 1 V at 6.8 dBm output power.

Place, publisher, year, edition, pages
IEEE Solid-State Circuits Society, 2012
Keyword
All digital, polar transmitter, transmitter, ADPLL, Delta Sigma
National Category
Telecommunications
Identifiers
urn:nbn:se:kth:diva-72240 (URN)10.1109/JSSC.2012.2186720 (DOI)000303329600010 ()2-s2.0-84860475717 (Scopus ID)
Projects
iPack
Funder
ICT - The Next Generation
Note

© 2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

QC 20120503

Available from: 2012-05-03 Created: 2012-01-31 Last updated: 2017-12-08Bibliographically approved

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  • ieee
  • modern-language-association-8th-edition
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Output format
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